The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: ADAPTIVE READ REFERENCE VOLTAGE DETERMINATION FOR MULTI-LEVEL NON-VOLATILE MEMORY.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharon (US PGPUB # 20140355340) in view of Horn (US Patent # 8638602 ).
With respect to independent claims 1, 12, 18 Sharon/Horn discloses: A method of a memory system, the method comprising:
performing a plurality of first read operations on multiple target memory cells based on a first set of read voltages to obtain a first set of read results [Multiple first representations of data are read from the non-volatile memory according to the first sets of read voltages, at 304 - Sharon 0057, fig 3 steps 302-304];
obtaining a first set of read reference voltages based on the first set of read results and level indicators of the multiple target memory cells [A first value of the first read voltage is selected based on first ECC related information from an error correction coding (ECC) decoder, at 306, the first ECC related information is responsive to the multiple first representations of the data - Sharon 0058, fig 3];
performing a plurality of second read operations on the multiple target memory cells based on a second set of read voltages to obtain a second set of read results [second read voltage is iteratively adjusted without adjusting the first read voltage to form second sets of read voltages, at 308…Multiple second representations of the data from the non-volatile memory are read according to the second sets of read voltages, at 310 - Sharon 0059-0060, fig 3 steps 308-310];
obtaining a second set of read reference voltages based on the second set of read results and level indicators of the multiple target memory cells [A second value of the second read voltage is selected based on second ECC related information from the ECC decoder, at 312. The second ECC related information responsive to the multiple second representations of the data - Sharon 0061, fig 3 steps 312]; and
performing a plurality of third read operations on the multiple target memory cells based on the first set of read reference voltages and the second set of read reference voltages to obtain a third set of read results [After selecting one of the trial values for VA, the read voltage update engine 140 may select another read voltage to adjust. A second graph 196 illustrates multiple trial values of VE that may each be used to read the data from the group 106. The resulting data may be decoded at the decoder 126 and a trial value selected for VE based on comparisons of actual or estimated errors. Each read voltage of the updated set of read voltages 146 may be updated by the read voltage update engine 140 in a similar manner as described with respect to VA – Sharon 0022. Accuracy of reading data stored in a data storage device may be improved by updating a set of read voltages used to read the stored data in order to reduce an estimated or actual bit error rate associated with reading the stored data. One or more read voltages may be adjusted while one or more other read voltages are held constant to generate multiple trial sets of read voltages. Multiple representations of the stored data are generated and correspond to reading the stored data using the multiple trial sets. Error correction coding (ECC) related information associated with the multiple representations may be used to select an updated value of the one or more read voltages. Updating of the read voltages may continue by holding the updated value constant while adjusting another read voltage – Sharon 0006; selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table - Horn abstract, fig 3].
Sharon does not explicitly teach performing a plurality of third read operations on the multiple target memory cells based on the first set of read reference voltages and the second set of read reference voltages to obtain a third set of read results, specifically in those words. However, Sharon’s updated set of read voltages, fig 1 element 146, contains the first and second read voltages which are used for ongoing reads – effectively a subsequent series of read operations on memory using both the first and second updated read reference voltages. Nevertheless, in the same field of endeavor Horn teaches “a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table”. In other words, once optimal reference voltage values are determined and stored per block/page, subsequent read operations are performed using those values by referencing a Vref table, and in effect executing a third set of read operations using first and second sets of read reference voltages to obtain third results which are read results using updated reference voltages.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform a plurality of third read operations on multiple target memory cells based on a first set of read reference voltages and a second set of read reference voltages to obtain a third set of read results in the invention of Sharon as taught by Horn because it would be advantageous for reading data while minimizing read errors and read inefficiencies (Horn col 1 lines 20-40) .
With respect to dependent claim 2, 13, 19 Sharon/Horn discloses obtaining data stored in the multiple target memory cells based on the third set of read results and level indicators of the multiple target memory cells [representations of data having a greater number of errors may generally require longer decoding (e.g., more iterations for convergence, longer error location search processing, etc.) than representations of data having fewer errors. The decoder 126 may be configured to fully decode a first representation of data and to store the decoding time for the first representation. For each subsequent representation of data, the decoder 126 may terminate decoding if the decoding time exceeds the stored decoding time, or may update the stored decoding time if the decoding time is less than the stored decoding time. The first ECC related information 142 may indicate one or more decoding times or relative decoding times of the representations 180-182 to enable the read voltage update engine 140 to identify a shortest of the decoding times of the representations 180-182 and to select a corresponding trial value of VA – Sharon 0031, 0037, 0039] [Vref testing using error counts – Horn abstract].
With respect to dependent claim 3, 14, 20 Sharon/Horn discloses wherein any one of the multiple target memory cells stores N bits of data, and wherein N is an integer greater than 1, the method of the memory system further comprising: obtaining a level indicator of each target memory cell based on the N bits of data stored in each target memory cell, wherein the multiple target memory cells include a first set of memory cells that store 2N1 different types of data and a second set of memory cells that store 2N-1 different types of data, and wherein a level indicator of the first set of memory cells is different from a level indicator of the second set of memory cells [Although the non-volatile memory 104 is described as a three bits per storage element (3BPC) MLC, in other implementations the non-volatile memory 104 may store a single bit per storage element (SLC), two bits per storage element (2BPC), four bits per storage element (4BPC), or any other number of bits per storage element. Although in the examples described above, five trial values of each read voltage are illustrated (e.g., N=5), in other implementations a number of trial values may be less than five or more than five – Sharon 0040; read voltage update engine 140 may select one or more read voltages for adjustment in a first iteration of a read voltage update process. The group 106 may store data in a page-by-page, non-interleaved manner, such that a first ECC codeword is stored in a first logical page of a physical page of the group 106 (e.g., a `lower` page corresponding to the least significant bit stored in each storage element of the physical page). A second ECC codeword may be stored in a second logical page of the physical page (e.g., a `middle` page corresponding to the middle bit stored in each storage element of the physical page). A third ECC codeword may be stored in a third logical page of the physical page (e.g., an `upper` page corresponding to the most significant bit stored in each storage element of the physical page) – Sharon 0024].
With respect to dependent claim 4, 15 Sharon/Horn discloses acquiring 2N-1-1 default read voltages of the second set of memory cells as first initial read voltages in the first set of read voltages; and acquiring 2N-1-1 default read voltages of the first set of memory cells as 2N-1-1 second initial read voltages in the second set of read voltages, wherein an M-th first initial read voltage in the 2N-1-1 first initial read voltages is less than an M-th second initial read voltage in the 2N-t-1second initial read voltages, and the M-th first initial read voltage in the 2N-t-1 first initial read voltages is greater than an (M-1)th second initial read voltage in the 2N-1-1second initial read voltages, wherein M is an integer greater than 1 [Sharon 0031-0032, 0063, 0078] [Horn col 3 lines 60-67, fig 2 52-58].
With respect to dependent claim 5, 16 Sharon/Horn discloses wherein each of the first read operations and the second read operations is a single-level read operation [Sharon 0040].
With respect to dependent claim 6, Sharon/Horn discloses wherein: the performing of the plurality of first read operations on the multiple target memory cells based on the first set of read voltages to obtain the first set of read results comprises: performing 2N-1-1 sets of first read operations on the multiple target memory cells based on the first set of read voltages, to obtain the first set of read results, wherein read voltages of each set of the 2N1Isetsof first read operations include one first initial read voltage and multiple first compensation read voltages obtained based on the first initial read voltage and a compensation value; and the performing of the plurality of second read operations on the multiple target memory cells based on the second set of read voltages to obtain the second set of read results comprises: performing 2N-1-1 sets of second read operations on the multiple target memory cells based on the second set of read voltages, to obtain the second set of read results, wherein read voltages of each set of the 2N-1I sets of second read operations include one second initial read voltage and multiple second compensation read voltages obtained based on the second initial read voltage and the compensation value [Sharon 0049, fig 2].
With respect to dependent claim 7, 17 Sharon/Horn discloses the obtaining of the first set of read reference voltages based on the first set of read results and level indicators of the multiple target memory cells comprises: obtaining 2N-1-1 different first read reference voltages in the first set of read reference voltages based on the first set of read results and inverted level indicators of the multiple target memory cells; and the obtaining of the second set of read reference voltages based on the second set of read results and level indicators of the multiple target memory cells comprises: obtaining 2N-1-1 different second read reference voltages in the second set of read reference voltages based on the second set of read results and level indicators of the multiple target memory cells [value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data - Sharon abstract … inversion may be part of logic circuitry used for establishing read reference values – Sharon 0043; the ECC related information may be used to select one of the trial values that results in a minimal (or maximal) detected value of an ECC related metric corresponding to the ECC related information. For example, an objective may be to determine a read threshold which minimizes the bit error rate. As another example, an objective may be to minimize ECC power, latency, throughput, or any other ECC related metric. Also it is not necessary to decode the codewords for determining an "optimal" read voltage. Other ECC related information may be used without fully decoding (e.g. computing the number of unsatisfied ECC parity-check equations, also known as syndrome weight, without full decoding, or BER estimation without decoding, as non-limiting examples) – Sharon 0021].
With respect to dependent claim 8 Sharon/Horn discloses wherein the obtaining of the 2N- 1 different first read reference voltages in the first set of read reference voltages based on the first set of read results and inverted level indicators of the multiple target memory cells comprises: obtaining a number of memory cells that store a first value in the first set of memory cells corresponding to each read voltage of an X-th set of first read operations in the 2N--I sets of first read operations based on read results of the X-th set of first read operations and inverted level indicators of the multiple target memory cells, wherein X is a positive integer; calculating differences between numbers of memory cells that store the first value in the first set of memory cells corresponding to two adjacent read voltages in the X-th set of first read operations, and determining an X-th first read reference voltage in the 2N-.1 different first read reference voltages based on a minimum of the differences; or calculating a ratio of the number of memory cells that store the first value in the first set of memory cells corresponding to each read voltage in the X-th set of first read operations to the number of memory cells in the first set of memory cells, and determining an X-th first read reference voltage in the 2N-1-1 different first read reference voltages based on a comparison of the ratio and Xx21-N [controller 120 includes a read voltage update engine 140 that is configured to generate the updated set of read voltages 146 based on ECC related information received from the decoder 126. To illustrate, a first graph 190 shows a histogram or distribution of storage element threshold values having clusters representing states Erase (Er), A, B, C, D, E, F, and G, in a 3-bit per cell (3BPC) multi-level cell (MLC) implementation. A set of read voltages VA, VB, VC, VD, VE, VF, and VG define boundaries between the states and may be used to determine a state of a storage element – Sharon 0019, fig 3-5].
With respect to dependent claim 9 Sharon/Horn discloses wherein the obtaining of the 2N-_1 different second read reference voltages in the second set of read reference voltages based on the second set of read results and level indicators of the multiple target memory cells comprises: obtaining a number of memory cells that store a first value in the second set of memory cells corresponding to each read voltage of a Y-th set of second read operations in the 2N-1-1 sets of second read operations based on read results of the Y-th set of second read operations and level indicators of the multiple target memory cells, wherein Y is a positive integer; and calculating differences between numbers of memory cells that store the first value in the second set of memory cells corresponding to two adjacent read voltages in the Y-th set of second read operations, and determining a Y-th second read reference voltage in the -I different second read reference voltages based on a minimum of the differences; or calculating a ratio of the number of memory cells that store the first value in the second set of memory cells corresponding to each read voltage in the Y-th set of second read operations to the number of memory cells in the second set of memory cells, and determining a Y-th second read reference voltage in the 2N-1-1 different second read reference voltages based on a comparison of the ratio and Yx21 [controller 120 includes a read voltage update engine 140 that is configured to generate the updated set of read voltages 146 based on ECC related information received from the decoder 126. To illustrate, a first graph 190 shows a histogram or distribution of storage element threshold values having clusters representing states Erase (Er), A, B, C, D, E, F, and G, in a 3-bit per cell (3BPC) multi-level cell (MLC) implementation. A set of read voltages VA, VB, VC, VD, VE, VF, and VG define boundaries between the states and may be used to determine a state of a storage element – Sharon 0019, fig 3-5].
With respect to dependent claim 10 Sharon/Horn discloses wherein the performing of the plurality of third read operations on the multiple target memory cells based on the first set of read reference voltages and the second set of read reference voltages to obtain the third set of read results comprises: using a first default read voltage of the first set of memory cells, a last default read voltage of the second set of memory cells, the first set of read reference voltages and the second set of read reference voltages as a third set of read voltages, wherein the first default read voltage of the first set of memory cells is less than a minimum first initial read voltage of the 2N-1-1 first initial read voltages, and the last default read voltage of the second set of memory cells is greater than a maximum second initial read voltage of the2Ni-1 second initial read voltages; and performing N sets of third read operations on the multiple target memory cells based on the third set of read voltages to obtain the third set of read results [Sharon 0031-0032, 0063, 0078] [Horn col 3 lines 60-67, fig 2 52-58].
With respect to dependent claim 11 Sharon/Horn discloses wherein performing each of the third read operations comprises: performing a first sub-read operation to obtain a first sub-read result, wherein a read voltage of the first sub-read operation includes a first read reference voltage; and performing a second sub-read operation to obtain a second sub-read result, wherein a read voltage of the second sub-read operation includes a second read reference voltage, wherein the obtaining of the data stored in the multiple target memory cells based on the third set of read results and level indicators of the multiple target memory cells comprises: obtaining one bit of data in the N bits of data stored in each target memory cell based on an operation result of the first sub-read result and inverted level indicators of the multiple target memory cells and an operation result of the second sub-read result and level indicators of the multiple target memory cells [Sharon 0042-0046].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
VENKITACHALAM US PGPUB # 20140029336 teaches in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-530p M-R.
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/Marwan Ayash/Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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