CTNF 19/182,522 CTNF 84639 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 18-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter. As per claim(s) 18-21, they are rejected because the applicant has provided evidence that the applicant intends the term "non-transitory computer-readable medium" to include non-statutory matter. The applicant describes a “non-transitory computer-readable medium” as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another . A non-transitory storage medium may be any available medium , or combination of multiple media, which can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer, or one or more processors, [0124]). The words "storage", "tangible", and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter. Since the specification describes "non-transitory computer-readable medium" as comprising both transitory and non-transitory media, the claim encompasses both and is therefore non-statutory. The examiner suggests amending the specification to remove “non-transitory” so that the term is not redefined to include non-statutory matter. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (U.S. Patent Application Publication No. 2022/0237079) in view of Kwatra (U.S. Patent Application Publication No. 2004/0098527) . Regarding claim 1, Cariello discloses a memory system, comprising: one or more memory devices (memory device 130, [0020-0030], fig. 1, 2); and processing circuitry coupled with the one or more memory devices (Host system 105, Host System Controller 106, [0105, 0019, 0020, 0022], fig. 1) and configured to cause the memory system to: set a first operand of a first register to a value, wherein the first operand indicates whether a fault has occurred in the memory system ([0039, 0051, 0067]). Cariello does not expressly disclose determining a value of a second operand of a second register, wherein the second operand indicates whether an alert output is driven based at least in part on the fault occurring in the memory system; and determining whether to drive the alert output based at least in part on the value of the first operand and the value of the second operand. Kwatra teaches that it was known in the art to determine a value of a second operand of a second register, wherein the second operand indicates whether an alert output is driven based at least in part on the fault occurring in the memory system ([0009, 0028, 0029], fig. 5); and determine whether to drive the alert output based at least in part on the value of the first operand and the value of the second operand ([0030, 0031], fig. 5). Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Cariello by including the alert output enabling as taught by Kwatra. One of ordinary skill would have been motivated to make the combination, in order to allow an I/O controller to alert an external controller using an enhanced SMBus implementation ([0009], Kwatra). Regarding claim 2, Cariello discloses wherein, to determine whether to drive the alert output, the processing circuitry is configured to cause the memory system to: refrain from driving the alert output based at least in part on the value of the first operand indicating that the fault has not occurred in the memory system ([0039, 0051, 0067]). Regarding claim 3, Kwatra discloses wherein, to determine whether to drive the alert output, the processing circuitry is configured to cause the memory system to: refrain from driving the alert output based at least in part on the value of the second operand indicating that the alert output is not driven based at least in part on the fault occurring in the memory system ([0009, 0028-0031], fig. 5). Regarding claim 4, Kwatra discloses wherein, to determine whether to drive the alert output, the processing circuitry is configured to cause the memory system to: drive the alert output based at least in part on the value of the first operand indicating that the fault has occurred and on the value of the second operand indicating that the alert output is driven based at least in part on the fault occurring ([0009, 0028-0031], fig. 5). Regarding claim 5, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: deactivate the alert output based at least in part on receiving a mode register read command to read the value of the first operand of the first register, on receiving a reset command, on a power source of the memory system being removed, on expiration of a timer, or a combination thereof ([0017]). Regarding claim 6, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: deactivate the alert output within a threshold quantity of time from reception of the mode register read command ([0024]). Regarding claim 7, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: receive a mode register read command to read the first operand of the first register; and reset the first operand of the first register to a default value based at least in part on receiving the mode register read command ([0024]). Regarding claim 8, Kwatra discloses wherein: the mode register read command is received within a first threshold quantity of time from driving the alert output, and the first threshold quantity of time is based at least in part on a type of the fault ([0017]). Regarding claim 9, Kwatra discloses wherein: the mode register read command is received within a first threshold quantity of time from the fault occurring in the memory system, and the first threshold quantity of time is based at least in part on a type of the fault ([0017]). Regarding claim 10, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: reset the first operand of the first register to a default value based at least in part on receiving a reset command, on a power source of the memory system being removed, on expiration of a timer, on receiving a mode register read command directed to the first register, or a combination thereof ([0028]). Regarding claim 11, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: receive, from a host device, a mode register write command to write the value of the second operand of the second register, wherein determining the value of the second operand is based at least in part on receiving the mode register write command ([0027]). Regarding claim 12, Kwatra discloses wherein the memory system is operating in an idle mode of operation and receiving the mode register write command is based at least in part on the memory system operating in the idle mode of operation ([0027]). Regarding claim 13, Kwatra discloses wherein the processing circuitry is further configured to cause the memory system to: reset the second operand of the second register to a default value based at least in part on receiving a reset command, on a power source of the memory system being removed, on receiving a mode register read command directed to the first register, on receiving a mode register read command directed to the second register, on expiration of a timer, or a combination thereof ([0028]). Regarding claim 14, Kwatra discloses wherein the fault comprises one of a per row activation (PRAC) limit exceeded, a write link error correction code (ECC) multi-bit error (MBE) fault, a write link error detection code (EDC) single bit error (SBE) fault, a write link EDC MBE fault, a write link ECC SBE attempt fault, an on-die ECC MBE fault, an on- die error correction and scrub (ECS) SBE threshold fault, a command address parity fault, a refresh rate change, or any combination thereof ([0017]). Regarding claim 15, Kwatra discloses wherein the first operand of the first register indicates whether at least one operand of a third register has been set to a first value ([0028]). Regarding claim 16, Kwatra discloses wherein: the second operand of the second register corresponds to the first operand of the first register ([0028]). Regarding claim 17, Kwatra discloses wherein: the second operand of the second register corresponds to a plurality of operands of the first register ([0028]). Regarding claim(s) 18 and 22, claim(s) 18 and 22 recite(s) substantially similar limitations to claim(s) 1 and is(are) therefore rejected using the same art and rationale set forth above. Regarding claim(s) 19-21, claim(s) 19-21 recite(s) substantially similar limitations to claim(s) 2-4 and is(are) therefore rejected using the same art and rationale set forth above . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA P LOTTICH whose telephone number is (571)270-3738. The examiner can normally be reached Mon - Fri, 9:00am - 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 5712723655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSHUA P LOTTICH/ Primary Examiner, Art Unit 2113 Application/Control Number: 19/182,522 Page 2 Art Unit: 2113 Application/Control Number: 19/182,522 Page 3 Art Unit: 2113 Application/Control Number: 19/182,522 Page 4 Art Unit: 2113 Application/Control Number: 19/182,522 Page 5 Art Unit: 2113 Application/Control Number: 19/182,522 Page 6 Art Unit: 2113 Application/Control Number: 19/182,522 Page 7 Art Unit: 2113
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