DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the response to election/restriction filed 7/28/2026. Claims 1-9 have been elected for further examination. Claims 10-19 have been canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Japanese patent JP 2001-68976.
Regarding claim 1, JP’s976 figure 1 shows An amplifying circuit, comprising: a floating inverter amplifier (21), wherein a threshold voltage of a transistor in the floating inverter amplifier varies corresponding to an environmental condition (threshold voltage of the transistors 22 and 23 varied due to manufacturing variations); and a voltage generating circuit (31), coupled with the floating inverter amplifier, and configured to provide an operating voltage to the floating inverter amplifier, wherein the operating voltage provided by the voltage generating circuit is linearly correlated to the threshold voltage (figure 3 shows OP, operating voltage varies in a linear relationship with a threshold voltage, translated specification pages 5-6), and the voltage generating circuit modulates a variation of the operating voltage to keep track with a variation of the threshold voltage (see translated specification pages 5-6) as called for in claim 1.
Regarding claim 7, JP’s976 figure 1 shows wherein the voltage generating circuit comprises a first current generating circuit (34), a second current generating circuit (38, 39) and a current-to-voltage converter circuit (33) , wherein the first current generating circuit is configured to generate a first operating current, the second current generating circuit is configured to generate a second operating current, and the current-to-voltage converter circuit is configured to generate the operating voltage according to a sum of the first operating current and the second operating current.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yabuuchi et al. (US 2008/0037358).
Regarding claim 1, Yabuuchi et al.’s figures 5-7 show An amplifying circuit, comprising: a floating inverter amplifier (WDR1-WDR3), wherein a threshold voltage of a transistor in the floating inverter amplifier varies corresponding to an environmental condition (threshold voltage of the transistors within WDR1-WDR3 varied due to manufacturing variations); and a voltage generating circuit (10), coupled with the floating inverter amplifier, and configured to provide an operating voltage to the floating inverter amplifier, wherein the operating voltage provided by the voltage generating circuit is linearly correlated to the threshold voltage (figure 7 shows the operating voltage varies in a linear relationship with a threshold voltage), and the voltage generating circuit modulates a variation of the operating voltage (VDDR) to keep track with a variation of the threshold voltage as called for in claim 1.
Regarding claim 7, Yabuuchi et al.’s figure 12 shows wherein the voltage generating circuit comprises a first current generating circuit (22), a second current generating circuit (26) and a current-to-voltage converter circuit (21, 20) , wherein the first current generating circuit is configured to generate a first operating current, the second current generating circuit is configured to generate a second operating current, and the current-to-voltage converter circuit is configured to generate the operating voltage according to a sum of the first operating current and the second operating current.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (US 2002/0131314).
Regarding claim 1, Watanabe et al.’s figures 7A and 7B show An amplifying circuit, comprising: a floating inverter amplifier (2’), wherein a threshold voltage of a transistor in the floating inverter amplifier varies corresponding to an environmental condition (threshold voltage of the transistors 22 and 23 varied due to manufacturing variations); and a voltage generating circuit (3), coupled with the floating inverter amplifier, and configured to provide an operating voltage to the floating inverter amplifier, wherein the operating voltage provided by the voltage generating circuit is linearly correlated to the threshold voltage (figure 7b shows the Vcont, operating voltage varies in a linear relationship with a threshold voltage), and the voltage generating circuit modulates a variation of the operating voltage (Vcont) to keep track with a variation of the threshold voltage as called for in claim 1.
Regarding claim 7, Watanabe et al.’s figure 25 shows wherein the voltage generating circuit comprises a first current generating circuit (CC), a second current generating circuit (TPR, TNR) and a current-to-voltage converter circuit (7, 8) , wherein the first current generating circuit is configured to generate a first operating current, the second current generating circuit is configured to generate a second operating current, and the current-to-voltage converter circuit is configured to generate the operating voltage according to a sum of the first operating current and the second operating current.
Allowable Subject Matter
Claims 2-6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, Japanese patent JP 2001-68976, Yabuuchi et al. (US 2008/0037358) and Watanabe et al. (US 2002/0131314) references, alone or in combination, fails to teach or fairly suggest he first current generating circuit comprises: a first multistage current mirror, comprising a first output end and configured to generate a first output current, wherein in response to that the first output current flows through the first output end, the first output end is configured to generate a first output voltage; and a first voltage-to-current converter circuit, coupled with the first output end to receive the first output voltage, and configured to convert the first output voltage into a first operating current; wherein the current-to-voltage converter circuit is coupled with the first voltage-to-current converter circuit to receive the first operating current, and configured to generate the operating voltage according to the first operating current, wherein the first operating current and the operating voltage are positively correlated to another threshold voltage of any transistor of the first multistage current mirror that the first output current flows through as called for in claim 2; the voltage generating circuit comprises a second current generating circuit and a current-to-voltage converter circuit, wherein the second current generating circuit comprises: a second multistage current mirror, comprising a second output end and configured to generate a second output current, wherein in response to that the second output current flows through the second output end, the second output end 3 is configured to generate a second output voltage; and a second voltage-to-current converter circuit, coupled with the second output end to receive the second output voltage, and configured to convert the second output voltage into a second operating current, wherein the current-to-voltage converter circuit is coupled with the second voltage-to-current converter circuit to receive the second operating current, and configured to generate the operating voltage according to the second operating current, wherein the second operating current and the operating voltage are positively correlated to another threshold voltage of any transistor of the second multistage current mirror that the second output current flows through as called for in claim 6; the current-to-voltage converter circuit comprises: a second current mirror, comprising a first end and a second end, wherein the second end of the second current mirror is configured to generate a second mirror current;4 a third current mirror, wherein a first end of the third current mirror is coupled with the second current generating circuit to output the second operating current, and a second end of the third current mirror is configured to generate a third mirror current; a fourth current mirror, wherein a first end of the fourth current mirror is coupled with the second end of the third current mirror to receive the third mirror current, and a second end of the fourth current mirror is coupled with the first end of the second current mirror and configured to generate a fourth mirror current; a fifth current mirror, wherein a first end of the fifth current mirror is coupled with the first current generating circuit to receive the first operating current, and a second end of the fifth current mirror is coupled with the first end of the second current mirror and configured to generate a fifth mirror current; and a second resistor, wherein the first end of the second current mirror is configured to receive the fourth mirror current and the fifth mirror current, and a first end of the second resistor is coupled with the second end of the second current mirror to receive the second mirror current, wherein in response to that the second mirror current sequentially flows from the second current mirror through the first end and a second end of the second resistor, the first end of the second resistor is configured to generate the operating voltage as called for in claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, Ooishi et al. (USP 6,292,015) shows inverters (X1-X3) and voltage generating circuit (Vref1to Vref4) coupled the invertes. Power supply selectors connecting the buffer power supply line to a main or sub power supply line and connecting the buffer ground line to a main or sub ground line in accordance with an output signal from a latch circuit are provided. Thus, leakage current in a logic circuit in which a logic level is not determined is reduced in the stand-by mode.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 9/5/2026
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