Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7 and 14 of U.S. Patent No. 12,282,433. Although the claims at issue are not identical, they are not patentably distinct from each other because they merely broaden the scope of the claims of the reference patent.
Refer to the following tables for each of the independent claims:
19/182,175
US 12,282,433
Same/different?
Claim 1. An apparatus, comprising:
Claim 1. An apparatus, comprising:
Same
a memory device; and
a memory device; and
Same
a memory controller coupled to the memory device, and comprising:
a memory controller, coupled to the memory device, comprising
Same
a cache, including a cache sequence controller configured to:
a cache, and configured to cause performance of a cache look-up operation associated with the cache, wherein the cache includes a cache sequence controller configured to:
Different
determine that a quantity of a given type of result of cache look-up operations associated with the cache satisfies a bypass threshold;
determine a quantity of a given type of result of cache look-up operations associated with the cache;
determine the quantity satisfies a bypass threshold; and
Different
cause performance of a bypass memory operation that bypasses the cache and accesses the memory device substantially contemporaneously with a cache look-up operation performed by the memory controller;
cause performance of a bypass memory operation, substantially contemporaneously with the performance of the cache look-up operation, that bypasses the cache and accesses the memory device;
Different
wherein performance of the cache look-up operation results in a cache miss; and
Different
cache-in any data associated with the performance of the bypass memory operation in the cache responsive to a determination that the cache is a clean cache.
wherein, responsive to a determination that the cache is a clean cache, the cache sequence controller is configured to cache-in any data associated with the performance of the bypass memory operation in the cache.
Different
19/182,175
US 12,282,433
Same/different?
Claim 10. A system, comprising:
Claim 7. A system, comprising:
Same
a memory device; and
a memory device; and
Same
a memory controller coupled to the memory device and configured to perform cache look-up operations associated with a cache responsive to host read requests, wherein the cache comprises:
a memory controller coupled to the memory device and configured to perform cache look-up operations associated with a cache responsive to host read requests associated with the memory device, wherein the cache comprises:
Different
A metric logic including counters, the metric logic configured to collect, within a threshold amount of time, metrics related to the cache look-up operations; and
Different
a cache sequence controller to:
a cache sequence controller to:
Same
determine, based on collected metrics, that a quantity of a given type of result of the cache look-up operations associated with the cache satisfies a bypass threshold;
determine, based on the collected metrics, a quantity of a given type of result of the cache look-up operations associated with the cache;
determine the quantity of the given type of result satisfies a bypass threshold;
Different
responsive to the determination that the quantity of the given type of result satisfies the bypass threshold:
responsive to the determination that the quantity of the given type of result satisfies the bypass threshold:
Same
perform a cache look-up operation to determine a cache hit or a cache miss corresponding to a host read request; and
perform a cache look-up operation to determine a cache hit or a cache miss corresponding to a host read request; and
Same
in parallel with performance of the cache look-up operation, initiate a bypass read operation to read data corresponding to the host read request from the memory device.
in parallel with performance of the cache look-up operation, initiate a bypass read operation to read data corresponding to the host read request from the memory device.
Same
19/182,175
US 12,282,433
Same/Different?
Claim 17. A method, comprising:
Claim 14. A method, comprising:
Same
receiving a read request at a controller coupled to a memory device;
receiving a read request at a controller coupled to a memory device;
Same
performing cache look-up operations on a cache of a central controller portion;
performing cache look-up operations on a cache of a central controller portion;
Same
collecting, over a threshold amount of time, metrics associated with performing the cache look-up operations;
Different
determining, based on metrics associated with performing the cache look-up operations, a quantity of cache misses resulting from performance of a quantity of consecutive cache look-up operations associated with the cache; and
determining, based on the collected metrics, a quantity of cache misses resulting from performance of a quantity of consecutive cache look-up operations associated with the cache;
Different
determining the quantity of cache misses satisfies a bypass threshold; and
Different
responsive to determining the quantity of cache misses satisfies a bypass threshold:
responsive to determining the quantity of cache misses satisfies the bypass threshold:
Different
bypassing the cache and accessing the memory device in response to a host access request; and
causing performance of a bypass read operation that bypasses the cache and accesses the memory device in response to a host access request; and
Different
causing performance of a cache look-up operation associated with the cache in response to the host access request.
causing performance of a cache look-up operation associated with the cache in response to the host access request substantially contemporaneously with the performance of the bypass read operation.
The tables above show that the independent claims of the present application correspond to the independent claims of the reference patent. It is clearly obvious that US Patent 12,282,433 substantially discloses the subject matter of claims 1, 10 and 17 of the instant application. Applicant merely broadens the scope of the instant application by deleting a few elements from US Patent 12,282,433.
The claims 2-9, 11-16 and 18-20 included in the statement of rejection but not specifically addressed in the body of the rejection have inherited the deficiencies of their parent claim and have not resolved the deficiencies. Therefore, they are rejected based on the same rationale as applied to their parent claims above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over De, US PGPub 2019/0384713, in view of Rohillah et al., US Patent 11,866,354, hereafter Rohillah.
With respect to claim 17, De teaches a method, comprising:
receiving a read request at a controller coupled to a memory device (pars. 53-54, the request for data being a read, received from the device controller 126 of par. 48);
performing cache look-up operations on a cache (par. 53, the on-die controller accessing the cache);
determining, based on metrics associated with performing the cache look-up operations, a quantity of cache misses resulting from performance of a quantity of consecutive cache look-up operations associated with the cache (pars. 53 and 57, the balancing circuit 304 in the balancing component determines the cache hit count (quantity of cache misses)); and
responsive to determining the quantity of cache misses satisfies a bypass threshold (par. 57, the balancing circuit 304 determines a relationship between the cache hit count and the total access count being greater than a predetermined threshold):
bypassing the cache and accessing the memory device in response to a host access request (pars. 55-57, the balancing circuit 304 directly communicated with the non-volatile memory device 408 in response to a relationship between the cache hit count and the total access count being greater than a predetermined threshold. The balancing circuit 304 directly communicating with the non-volatile storage bypasses the communication with the cache 410. Note that this is a contingent limitation based on the condition “responsive to determining the quantity of cache misses satisfies a bypass threshold,” and is not required to occur.); and
causing performance of a cache look-up operation associated with the cache in response to the host access request (par. 55-57. Note that this is a contingent limitation based on the condition “responsive to determining the quantity of cache misses satisfies a bypass threshold,” and is not required to occur.).
De teaches performing cache look-up operations on a cache, but fails to teach the cache is of a central controller portion.
Re teaches:
a cache (fig. 1, cache 120) of a central controller portion (fig. 1, cache controller circuitry 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have modified De to incorporate the teaching of Rohillah such that the memory controller of De that communicates with the cache would include the cache and the cache controller circuitry of Rohillah that receives various performance metrics from the cache. The motivation is to switch between insertion policies at a given cache level based on various performance metrics, as disclosed in Rohillah col 3, lines 3-4.
With respect to claim 19, De and Rohillah teach the limitations of the parent claim. De further teaches the method of claim 17, wherein data associated with the performance of the bypass read operation is selectively utilized based on a type of respective result of the cache look-up operations (pars. 55-57, the balancing circuit 304 directly communicated with the non-volatile memory device 408 in response to a relationship between the cache hit count and the total access count being greater than a predetermined threshold. The balancing circuit 304 directly communicating with the non-volatile storage bypasses the communication with the cache 410).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over De and Rohillah as applied to claim 17 above, and further in view of Polishuk et al., US PGPub 2023/0305960, hereafter “Polishuk.”
With respect to claim 18, De and Rohillah teach the limitations of the parent claim, but fail to teach determining a quantity of consecutive cache misses resulting from performance of the plurality of consecutive cache look-up operations, and determining the quantity of consecutive cache misses exceeds the bypass threshold. Polishuk further teaches the method of claim 17, wherein the cache look-up operations comprise a plurality of consecutive cache look-up operations, and further comprising:
determining a quantity of consecutive cache misses resulting from performance of the plurality of consecutive cache look-up operations (par. 77, 79, and 81, and figs 6a-6c, the sequences 600-602 of respective communications between a cache controller 620, a snoop filter controller, and a cache array 640. The cache controller 620 participates in lookup 612, and a miss message 613 is generated to indicate to the cache controller 620 that no such corresponding entry has been found by the lookup 612),
De teaches determining the quantity of cache misses exceeds the bypass threshold (par. 57, the balancing circuit 304 determines a relationship between the cache hit count and the total access count being greater than a predetermined threshold), so the combination of De with Polishuk teaches determining the quantity of consecutive cache misses exceeds the bypass threshold, as Polishuk teaches determining a quantity of consecutive cache misses (pars. 77, 29, and 81, as discussed above)
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: De, Rohillah, and the other prior art of record fail to teach wherein the metrics are collected over a threshold amount of time, and wherein the threshold amount of time is variable based on a hit rate or a miss rate of the cache look-up operations.
Independent claims 1 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7 and 14 of U.S. Patent No. 12,282,433. If the Applicant were to resolve the double patenting rejection through a terminal disclaimer, claims 1-16 would be allowable, as they contain the similar allowable subject matter as that of the parent application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Moyer et al., US Patent 12,204,454 teaches bypassing cache insertion. Walker, US Patent 11,853,224 teaches a filter for storing to cache. Jain et al., US PGPub 2023/0341922 teaches dynamic cache bypass for power savings. Mounes-Toussi, US Patent 6,651,143 teaches a cache bypass. Mirza, US Patent 5,625,793 teaches automatic cache bypass for instructions exhibiting poor cache hit ration.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights