Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Har-Shai et al.
PNG
media_image1.png
672
550
media_image1.png
Greyscale
PNG
media_image2.png
443
569
media_image2.png
Greyscale
PNG
media_image3.png
452
590
media_image3.png
Greyscale
With respect to claim 1, Har-Shai et al. (US 11620885) discloses a circuit for driving a gate of a power semiconductor device (SW2 fig. 1e), comprising: a plurality of switching cells (103a), each switching cell of the plurality of switching cells operable in a series-state and parallel-state and comprising: an output coupled to a first terminal of an energy storage component (i.e. C1) ; a first input (19a input to 109) coupled to a node selected from the output of another of the plurality of switching cells and an energy source (at Istring and load), at least one first switching device coupled between the output and the first input (103a at 19a), at least one second switching device coupled to a second terminal of the energy storage component and to the first input (103 at 19b), and at least one third switching device (other 103) coupled to the second terminal of the energy storage component and to an energy source or a second output of another of the plurality of switching cells (103);a controller (109 central line communicator) that generates control signals (Central unit 109 may also serve as to send appropriate control signals to circuits 103 ) to configure each of the plurality of switching cells (103s) in either the series-state or the parallel-state; and, an output of a switching cell (at IBout) being configured to couple to the gate (i.e. via B1 or B2) of the power switching device.
With respect to claim 2, the circuit above discloses the circuit of claim 1, wherein the plurality of switching cells (103s) and the controller (i.e. 109) are components of a same chip (i.e fig. 1a).
With respect to claim 3, the circuit above disclose the circuit of claim 2, a plurality of the energy storage components (C1, charge storage device) being on the same chip as the switching devices (103).
With respect to claim 5, the circuit above discloses the circuit of claim 1, each energy storage component of the plurality of energy storage components being a capacitor (C1).
With respect to claim 6, the circuit above discloses the circuit of claim 5, wherein the control signals are sequenced by the controller (109) to cause a voltage at the gate to increase or decrease in a plurality of voltage steps ( Here the voltage increase or decrease are interpreted as the appropriate control signals “ central unit 109 may sense the input of load 105 so as to measure input voltage (VT) and input current (IL) to load 105. Central unit 109 may also be operatively attached to a network 115, e.g. Internet for the purposes of remote monitoring or control of system 10. Central unit 109 may also serve as to send appropriate control signals to circuits 103 based on previously determined operating criteria of power harvesting system 10.”).
With respect to claim 7, the circuit above discloses the circuit of claim 6, wherein a time duration of a transition on the gate is adjustable by the controller (here, the opening and closing of switches is adjustable based on the sufficiency of the voltage. Which is controlled by 109 and the photovoltaic cell. ).
With respect to claim 8, the circuit above discloses the circuit of claim 6, wherein a time duration of a transition on the gate is configured by the controller (109) to mitigate one or both of ringing and overshoot (see column 3 lines 55-60) of a voltage waveform at the gate.
With respect to claim 9, the circuit above discloses the circuit of claim 5, the plurality of capacitors (C1) capable of delivering energy to the gate and to recover energy from the gate (See fig. 1f and “As soon as sufficient light irradiates panels 101 and current flows in photovoltaic string 107, zener diode Z1 has voltage drop VZ1 which charges capacitor C1 so as to provide V.sub.logic to controller 130. When capacitor C1 is being charged during time T1, the voltage drop of the output across nodes X and Y is the voltage (VZ1) of zener Z1 plus the voltage across the integral diode of switch SW2. When V.sub.logic is sufficient, all the active circuitry in controller 130 starts to work which closes switches SW2 and SW3 for a time period T2. Time period T2 may be much greater than time period T1. Switches SW2 and SW3 being closed (during time T2) gives a voltage drop across nodes X and Y. Therefore, with the longer time period T2 and the voltage drop across nodes X and Y, overall, less power may be lost by bypass circuit 121. Controller 130 continues to work until the voltage (V.sub.logic) of charge storage device C1 drops below a minimal voltage and once again charge storage device C1 has voltage drop VZ1 from zener Z1 which charges capacitor C1 so as to provide V.sub.logic. Once sufficient power is generated from panels 101, controller 130 can get a voltage supply from a panel 101 at nodes X and Y.”).
With respect to claim 10, the circuit above discloses the circuit of claim 5, the switching devices (SW2 and SW3) of the plurality of switching cells (103) configurable by the controller (109) to couple the capacitors (C1) of the plurality of switching cells in either series or parallel to control voltage at the gate.
With respect to claim 11, the circuit above discloses the circuit of claim 5 further comprising one or more energy sources (101, photovoltaic cells) either: couplable in parallel with the plurality of energy storage devices (C1); or coupled to a connecting node of the plurality of energy storage devices.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Har-Shai et al. (US 11620885).
With respect to claim 4, the prior art of record discloses the circuit of claim 2, having an energy storage component (i.e. 105 battery) being off-chip from the switching devices but fails to disclose a plurality of energy storage components.
It would would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have multiple batteries as energy storage components for the purpose of extending the capacity of the circuit.
Allowable Subject Matter
Claims 12-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 12, the prior art of record fails to suggest or disclose a switched-capacitor driver powered by a first rail and a second rail, the switched- capacitor driver controllable by a control input , the driver comprising :at least a first and a second capacitive boost stage, each capacitive boost stage comprising: a first- parallel switch transistor configured to controllably charge a first terminal of a capacitor, a second parallel switch transistor configured to controllably couple a second input to a second terminal of the capacitor, and a series transistor configured to controllably couple the second terminal of the capacitor to a first input; each capacitive boost stage having a parallel state with the first and second parallel switch transistor conducting and the series transistor nonconducting, and a series state with the first and second parallel switch transistor nonconducting and the series transistor conducting ;a first output transistor coupled to controllably couple the first terminal of the capacitor of the second capacitive boost stage to an output, the output configured to drive a gate of a power transistor; a second output transistor coupled to controllably couple the second terminal of the capacitor of the second capacitive boost stage to the output; a delay unit coupled to transition the first output transistor to an on state, transition the first capacitive boost stage from the parallel state to the series state, and transition the second capacitive boost stage from the parallel state to the series state, in a sequence beginning after receiving an on transition of the control input, the delay unit configured such that no two of the first output transistor ,the first capacitive boost stage, and the second capacitive boost stage transition simultaneously; wherein the first input of the first capacitive boost stage is coupled to the first rail, and the second input of the first capacitive boost stage is coupled to the second rail; and the series transistor of the second capacitive boost stage is coupled to the first terminal of the capacitor of the first capacitive boost stage.
Here, the details including the delay unit, the details of the charging the first and second boost stages including the operation and the couplings are not disclosed in the prior art.
With respect to claims 13-16, these claims are allowable on the basis of their dependence on claim 12.
With respect to claim 17, the prior art of record fails to suggest or disclose a method of driving a gate of a driven transistor comprising: providing a chain of capacitive boost stages, the chain of boost stages comprising at least a first and a last capacitive boost stage, each capacitive boost stage comprising: a first-input parallel switch transistor configured to controllably couple a first input to a first terminal of a capacitor, a second-input parallel switch transistor configured to controllably couple a second input to a second terminal of the capacitor, and a series transistor configured to controllably couple the second terminal of the capacitor to the first input; each capacitive boost stage having a parallel state with the first-input and second-input parallel switch transistors conducting and the series transistor nonconducting, and a series state with the first and second parallel switch transistor nonconducting and the series transistor conducting; providing a first output transistor that couples the first terminal of the capacitor of the last boost stage to an output, the output configured to drive the gate of the driven transistor; a second output transistor couples the second terminal of the capacitor of the last boost stage to the gate of the driven transistor; upon receiving an on transition of a control input, in sequence performing: turning on the first output transistor and turn off the second output transistor, and sequentially switching each of the capacitive boost stages to the series state; and upon receiving an off transition of the control input, in sequence performing: sequentially switching each of the capacitive boost stages to the parallel state; and turning on the second output transistor and turning off the first output transistor.
Here, the details of upon receiving an on transition of a control input, in sequence performing: turning on the first output transistor and turn off the second output transistor, and sequentially switching each of the capacitive boost stages to the series state; and upon receiving an off transition of the control input, in sequence performing: sequentially switching each of the capacitive boost stages to the parallel state; and turning on the second output transistor and turning off the first output transistor are not disclosed in the prior art.
With respect to claims 18-19, these claims are allowable on the basis of their dependence on claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2836
Prosecution Insights