DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2016/0293103). All reference is to Kimura unless otherwise indicated.
Regarding Claim 1 (Original), Kimura teaches a pixel circuit, comprising
a driving circuit [fig. 2 @DRT],
a data writing circuit [fig. 6B @Vsig and SST],
a storage circuit [fig. 2 @CS] and
a first reset circuit [fig. 5B @Vini and SST], wherein
the driving circuit [fig. 2 @DRT] comprises a control terminal [gate], a first terminal and a second terminal [fig. 2 illustrates], and is configured to control a driving current flowing [¶0039] through the first terminal and the second terminal for driving a light-emitting element [fig. 6B @ELD] to emit light;
the data writing circuit [fig. 6B @Vsig and SST] is configured to write a data signal [fig. 2 @Vsig] to the control terminal of the driving circuit under a control of a first scanning signal [fig. 2 @SLA];
the storage circuit is configured to store the data signal [¶0072, “The driving transistor DRT outputs a drain current Ie of a current amount corresponding to the gate control voltage written to the capacitor element CS”];
the first reset circuit [fig. 5B @Vini and SST] is configured to apply a first initialization voltage [fig. 6A @Vini] to the control terminal of the driving circuit [fig. 6A @DRT, fig. 2 @SLA] under a control of a first reset control signal [fig. 2 @SLA];
the first reset circuit [fig. 2 @SST] comprises an N-type [¶0045] oxide thin film transistor [it is well known in the art to implement a switching transistor as an oxide semiconductor thin film transistor (TFT) because of their superior switching characteristics and low leakage current]; wherein
the pixel circuit further comprises a third reset circuit [fig. 2 @RST2],
wherein the third reset circuit is configured to apply a holding voltage [figs. 2 and 6B @Vrst2] to the first terminal of the driving circuit [figs. 2 and 6B @DRT] under a control of a third reset control signal [figs. 2 and 4 @RG2]; and wherein
the third reset control signal [fig. 4 @RG2_k] and the first reset control signal [fig. 4 @SG_k] both are turn-on signals in at least part of a time period [fig. 4 @Pw], and the first reset circuit [fig. 4 @SG_k] is turned on earlier [fig. 4 illustrates claimed structure] than the third reset circuit [fig. 4 @RG1_k].
Regarding Claim 2 (Original), Kimura teaches the pixel circuit according to Claim 1, wherein
an N-type thin film transistor [¶0040, “the driving transistor DRT is an n channel type”] comprised in the driving circuit is a first transistor [fig. 2 @DRT],
a gate electrode of the first transistor serves as the control terminal [¶0039, “In the driving transistor DRT, a drain current is controlled by a gate voltage”] of the driving circuit [¶0038, “The gate of the driving transistor DRT is electrically connected to the first signal line VSL via the first switch SST”],
a first electrode of the first transistor [fig. 2 @DRT] serves as the first terminal of the driving circuit [directly connected to fig. 2 @BCD], and
a second electrode of the first transistor [fig. 2 @DRT] serves as the second terminal of the driving circuit [directly connected to fig. 2 @BCD].
Regarding Claim 3 (Original), Kimmel teaches the pixel circuit according to Claim 1, wherein
an N-type thin film transistor [fig. 2 @SST] comprised in the data writing circuit is a second transistor,
a gate electrode of the second transistor [fig. 2 @SST] is connected to a first scanning signal terminal to receive the first scanning signal [fig. 2 @SG],
a first electrode of the second transistor [fig. 2 @SST] is connected to a data signal terminal to receive the data signal [fig. 2 @Vsig], and
a second electrode of the second transistor [fig. 2 @SST] is connected to the control terminal of the driving circuit [fig. 2 @DRT].
Regarding Claim 4 (Original), Kimura teaches the pixel circuit according to Claim 1, wherein
the storage circuit comprises a storage capacitor [fig. 2 @CS],
a first electrode of the storage capacitor is connected to the control terminal of the driving circuit [fig. 2 @DRT], and
a second electrode of the storage capacitor [fig. 2 @CS] is connected to the second terminal of the driving circuit [fig. 2 @DRT].
Regarding Claim 10 (Original), Kimura teaches the pixel circuit according to Claim 1, wherein
the third reset circuit comprises a sixth transistor which is an N-type thin film transistor [fig. 2 @RST2],
a gate electrode of the sixth transistor [fig. 2 @RST2] is connected to a third reset control signal terminal to receive the third reset control signal [fig. 2 @RG2],
a first electrode of the sixth transistor [fig. 2 @RST2] is connected to a holding voltage terminal to receive the holding voltage [fig. 2 @Vrst2], and
a second electrode of the sixth transistor [fig. 2 @RST2] is connected to the first terminal of the driving circuit [fig. 2 @DRT].
Regarding Claim 18 (Original), Kimura teaches a display panel [fig. 1 @102], comprising
a plurality of pixel units [fig. 1 @PX] arranged in an array [¶0032, “The display device 100 includes a display part 110 arranged with a plurality of pixels PX. Although the pixels PX are shown In FIG. 1 arranged 4×4, actually an arbitrary number of pixels PX are arranged in a row direction and column direction”], wherein
each of the plurality of pixel units comprises a pixel circuit [fig. 2], wherein
the pixel circuit comprises a driving circuit [fig. 2 @DRT], a data writing circuit [fig. 6B @Vsig and SST], a storage circuit [fig. 2 @CS] and a first reset circuit [fig. 5B @Vini and SST], wherein
the driving circuit [fig. 2 @DRT] comprises a control terminal [gate], a first terminal and a second terminal [fig. 2 illustrates], and is configured to control a driving current flowing [¶0039] through the first terminal and the second terminal for driving a light-emitting element [fig. 6B @ELD] to emit light;
the data writing circuit [fig. 6B @Vsig and SST] is configured to write a data signal [fig. 2 @Vsig] to the control terminal of the driving circuit under a control of a first scanning signal [fig. 2 @SLA];
the storage circuit is configured to store the data signal [¶0072, “The driving transistor DRT outputs a drain current Ie of a current amount corresponding to the gate control voltage written to the capacitor element CS”];
the first reset circuit [fig. 5B @Vini and SST] is configured to apply a first initialization voltage [fig. 6A @Vini] to the control terminal of the driving circuit [fig. 6A @DRT, fig. 2 @SLA] under a control of a first reset control signal [fig. 2 @SLA];
the first reset circuit [fig. 2 @SST] comprises an N-type [¶0045] oxide thin film transistor [it is well known in the art to implement a switching transistor as an oxide semiconductor thin film transistor (TFT) because of their superior switching characteristics and low leakage current]; wherein
the pixel circuit further comprises a third reset circuit [fig. 2 @RST2],
wherein the third reset circuit is configured to apply a holding voltage [figs. 2 and 6B @Vrst2] to the first terminal of the driving circuit [figs. 2 and 6B @DRT] under a control of a third reset control signal [figs. 2 and 4 @RG2]; and wherein
the third reset control signal [fig. 4 @RG2_k] and the first reset control signal [fig. 4 @SG_k] both are turn-on signals in at least part of a time period [fig. 4 @Pw], and the first reset circuit [fig. 4 @SG_k] is turned on earlier [fig. 4 illustrates claimed structure] than the third reset circuit [fig. 4 @RG1_k].
Claim 5-9, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Im (US 2021/0134227). All reference is to Kimura unless otherwise directed.
Regarding Claim 5 (Original), Kimura teaches the pixel circuit according to Claim 1
Kimura does not teach the N-type oxide thin film transistor comprised in the first reset circuit is a third transistor, a gate electrode of the third transistor is connected to a first reset control signal terminal to receive the first reset control signal, a first electrode of the third transistor is connected to a first initialization voltage terminal to receive the first initialization voltage, and a second electrode of the third transistor is connected to the control terminal of the driving circuit
Im teaches an N-type oxide thin film transistor comprised in the first reset circuit is a third transistor [fig. 14 @Q3, Im: ¶0095, “The transistors T1 to T7 may be N-type (NMOS) transistors”],
a gate electrode of the third transistor [fig. 14 @Q3] is connected to a first reset control signal terminal to receive the first reset control signal [fig. 14 @GBL],
a first electrode of the third transistor [fig. 14 @Q3] is connected to a first initialization voltage terminal to receive the first initialization voltage [fig. 14 @VREFL], and
a second electrode of the third transistor is connected to the control terminal [fig. 14 @N1] of the driving circuit [fig. 14 @N1]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of applying a voltage to the gate of a driving transistor as taught by Im into the display panel taught by Kimura in order to measure the driving transistor threshold voltage.
Regarding Claims 6 and 19 (Original), Kimura teaches the pixel circuit according to Claim 1 and the display panel according to Claim 18
Kimura does not teach the pixel circuit further comprises a second reset circuit, wherein the second reset circuit is configured to apply a second initialization voltage to the second terminal of the driving circuit under a control of a second reset control signal
Im teaches a second reset circuit [fig. 14 @Q4], wherein
the second reset circuit [fig. 14 @Q4] is configured to apply a second initialization voltage [fig. 14 @VINTL] to the second terminal [fig. 14 @N2] of the driving circuit [fig. 14 @Q1] under a control of a second reset control signal [fig. 14 @GIL]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of applying an initialization voltage to the cathode of the light emitting device as taught by Im into the display panel taught by Kimura in order to prevent current flow through the light emitting device while the driving transistor threshold voltage is measured.
Regarding Claims 7 and 20 (Original), Kimura in view of Im teaches the pixel circuit according to Claim 6 and the display panel according to Claim 19, wherein
the second reset circuit [Im: fig. 14 @Q4] comprises a fourth transistor [Q4] which is an N-type thin film transistor [Im: ¶0095, “The transistors T1 to T7 may be N-type (NMOS) transistors”],
a gate electrode of the fourth transistor [Im: fig. 14 @Q4] is connected to a second reset control signal terminal to receive the second reset control signal [Im: fig. 14 @GIL],
a first electrode of the fourth transistor [Im: fig. 14 @Q4] is connected to a second initialization voltage terminal to receive the second initialization voltage [Im: fig. 14 @VINTL], and
a second electrode of the fourth transistor [Im: fig. 14 @Q4] is connected to the second terminal of the driving circuit [Im: fig. 14 @Q1].
Regarding Claim 8 (Original), Kimura in view of Im teaches the pixel circuit according to Claim 6, further comprising
a first light emission control circuit [fig. 2 @BCT], wherein
the first light emission control circuit is configured to apply a first power supply voltage [fig. 2 @PVDD] to the first terminal of the driving circuit [fig. 2 @DRT] under a control of a first light emission control signal [fig. 2 @BG].
Regarding Claim 9 (Original), Kimura in view Im teaches the pixel circuit according to Claim 8, wherein
the first light emission control circuit [Im: fig. 14 @Q5] comprises a fifth transistor which is an N-type thin film transistor [Im: fig. 14 @Q5, ¶0095, “The transistors T1 to T7 may be N-type (NMOS) transistors”],
a gate electrode of the fifth transistor [Im: fig. 14 @Q5] is connected to a first light emission control terminal to receive the first light emission control signal [Im: fig. 14 @GWL],
a first electrode of the fifth transistor [Im: fig. 14 @Q5] is connected to a first power supply terminal to receive the first power supply voltage [Im: fig. 14 @ELVDDL], and
a second electrode of the fifth transistor is connected to the first terminal of the driving circuit [Im: fig. 1 @Q1].
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Im and Cho (US 2022/0320253). All reference is to Kimura unless otherwise indicated.
Regarding Claim 11 (Original), Kimura in view of Im teaches the pixel circuit according to Claim 6
Kimura in view of Im does not teach a second light emission control circuit, wherein the second light emission control circuit is configured to apply the driving current to a first electrode of the light-emitting element under a control of a second light emission control signal
Cho teaches a second light emission control circuit [fig. 3 @T6], wherein
the second light emission control circuit is configured to apply the driving current to a first electrode of the light-emitting element [fig. 3 @OLED] under a control of a second light emission control signal [fig. 3 @En]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate a second light emission control circuit, as taught by Cho into the pixel circuit taught by Kimura in view of Im in order to endure when the emission control signals are off, current will not flow through the light emission element.
Regarding Claim 12 (Original), Kimura in view of Im and Cho teaches the pixel circuit according to Claim 11, wherein
the second light emission control circuit comprises a seventh transistor [Cho: fig. 3 @T6] which is an N-type thin film transistor [Cho: ¶0133, “As a person having ordinary skill in the art would appreciate, however, the first to seventh transistors T1 to T7 may be n-type MOSFETs, with a corresponding difference in operation and connection”],
a gate electrode of the seventh transistor [Cho: fig. 3 @T6] is connected to a second light emission control terminal [Cho: fig. 3 @EL] to receive the second light emission control signal [Cho: fig. 3 @En],
a first electrode of the seventh transistor is connected to the second terminal of the driving circuit [Cho: fig. 3 @T1], and
a second electrode of the seventh transistor [Cho: fig. 3 @ T6] is connected to the first electrode of the light-emitting element [Cho: fig. 3 @OLED].
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Toyomura (US 2015/0294623). All reference is to Kimura unless otherwise indicated.
Regarding Claim 13 (Original), Kimura teaches the pixel circuit according to Claim 1
Kimura does not teach a voltage transmission circuit, wherein the voltage transmission circuit is configured to transmit a second power supply voltage to the first terminal of the driving circuit in a first time period, and to transmit a first power supply voltage different from the second power supply voltage to the first terminal of the driving circuit in a second time period, under a control of a voltage transmission control signal
Toyomura teaches a voltage transmission circuit [fig. 16 @33], wherein
the voltage transmission circuit is configured to transmit a second power supply voltage [fig. 15 @Vini] to the first terminal of the driving circuit [fig. 16 @ DRT] in a first time period [fig. 15 @P1], and
to transmit a first power supply voltage [fig. 15 @Vccp] different from the second power supply voltage to the first terminal of the driving circuit [fig. 16 @DRT] in a second time period [fig. 15 @P2], under a control of a voltage transmission control signal [fig. 16 @ Ss]
Before the application was filed it would have been obvious to one of ordinary skill in the art to control the voltage applied to a first terminal of a driving transistor as taught by Toyomura into the pixel circuit taught by Kimura in order to supply and initialization voltage and a driving voltage over the same power line.
Regarding Claim 14 (Original), Kimura in view of Toyomura teaches the pixel circuit according to Claim 13, wherein
the voltage transmission circuit comprises an eighth transistor [Toyomura: fig. 16 @34] which is an N-type thin film transistor,
a gate electrode of the eighth transistor [Toyomura: fig. 16 @34] is connected to a voltage transmission control signal terminal to receive the voltage transmission control signal [Toyomura: fig. 16 @Ss],
a first electrode of the eighth transistor [Toyomura: fig. 16 @34] is connected to a first power supply terminal [Toyomura: fig. 16 @Vccp], and
a second electrode of the eighth transistor [Toyomura: fig. 16 @34] is connected to the first terminal of the driving circuit [Toyomura: fig. 16 @DRT], and
the first power supply terminal is configured to provide the second power supply voltage [Toyomura: fig. 15 @Vini] in the first time period [Toyomura: fig. 15 @P1], and
to provide the first power supply voltage [Toyomura: fig. 15 @Vccp] in the second time period [Toyomura: fig. 15 @P2].
Allowable Subject Matter
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1000-1700 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Douglas Wilson/Primary Examiner, Art Unit 2622