DETAILED ACTION
This action is in response to the filing 04/25/2025. Claims 1-18 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claim 18 is objected to.
Claims 1-2, 4, 6, and 8 are rejected under 35 U.S.C. 102.
Claims 9, 12, 14-15, and 18 are rejected under 35 U.S.C. 103.
Claims 3, 5, 7, 10-11, 13, and 16-17 contain allowable subject matter but are objected to as being dependent upon a rejected base clam.
Claim Objections
Claim 18 is objected to because of the following informalities: Claim 18 appears to recite the same limitation twice. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, and 8 are rejected under 35 U.S.C. 102 as being unpatentable over Ditty et al. (U.S. PGPub No. 20190258251).
Regarding Claim 1, Ditty teaches,
A troubleshooting method, applied to a chip, wherein the chip comprises a hardware unit, a first processor, and a second processor (errors are detected in SoC hardware (5054) ("hardware unit") [0456]; L1SS safety supervisor (5012(1), also called 5014(1) [0439]) ("second processor") operating on processor (5050) [0426]; L2SS safety supervisor (5014(2)) ("first processor") operating on a different processor than the L1SS safety supervisor [0439]; L1SS and L2SS are on the same SoC [0451]; also see Fig. 33), and the method comprises:
receiving, by the first processor, a hardware fault reported by the hardware unit (the L2SS safety supervisor (5014(2)) ("first processor") is directly notified of a hardware fault [0443]);
and receiving, by the second processor, the hardware fault reported by the hardware unit (a safety watchdog (5010) detects errors or faults and reports these faults to the L1SS safety supervisor (5014(1)) ("second processor") [0425-0426]).
Regarding Claim 2, Ditty teaches,
The method according to claim 1, wherein the method further comprises: sending, by the first processor, the hardware fault to an off-chip processor (L3SS safety supervisor (5014(3)) ("off-chip processor") receives detected errors/failures from L2SS safety supervisor (5014(2)) ("first processor"), where (5014(3)) may be located on a different silicon ("off-chip") [0443]).
Regarding Claim 4, Ditty teaches,
The method according to claim 1, wherein the chip further comprises an error management unit (hardware security module (5096) [see Fig. 38]),
and the receiving, by the first processor, a hardware fault reported by the hardware unit comprises: receiving, by the error management unit, the hardware fault reported by the hardware unit (the hardware security module (5096) [Fig. 38] receives the fault [0456]);
and sending, by the error management unit, the hardware fault to the first processor and/or an off-chip processor (the hardware security module (5096) [Fig. 38] notifies the L2SS safety supervisor (5014(2)) of the error and notifies the L3SS safety supervisor (5014(3)) of the error [0456; Fig. 38]).
Regarding Claim 6, Ditty teaches,
The method according to claim 1, wherein the method further comprises: detecting, by the second processor, the hardware fault of the hardware unit (a safety watchdog (5010) detects errors or faults and reports these faults to the L1SS safety supervisor (5014(1)) ("second processor") [0425-0426]);
and reporting, by the second processor, the hardware fault of the hardware unit to the first processor (L1SS safety supervisor (5014(1)) reports the error condition to the L2SS(2) safety supervisor (5014(2)) [0454]).
Regarding Claim 8, Ditty teaches,
The method according to claim 1, wherein the first processor is a functional security processor, and the second processor is an application processor (L2SS safety supervisor (5014(2)) is also described as a security supervisor (5014(2)) ("functional security processor") [0448], where L2SS may be on it's own distinct processor (5052) [0439]; L1SS safety supervisor (5014(1)) ("second processor") is on processor 5050 that executes application processes ("application processor") [0425]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ditty et al. (U.S. PGPub No. 20190258251) in view of Gong et al. (DE 112018007637 T5, supplied by Examiner).
Regarding Claim 9, Ditty teaches,
A troubleshooting method, applied to a chip, wherein the chip comprises a hardware unit and an error management unit, the error management unit comprises a logic circuit …, and the method comprises: receiving, by the logic circuit, a hardware fault reported by the hardware unit (a hardware fault is detected and the fault is notified to a hardware security module of a SoC ("logic circuit") [0456]);
and sending … the hardware fault to an off-chip processor through a direct- connection hardware channel, wherein the direct-connection hardware channel is a hardware channel between the error management unit and the off-chip processor (errors are detected in SoC hardware (5054) ("hardware unit") [0456]; L3SS safety supervisor (5014(3)) ("off-chip processor") receives error information directly via a PCIe link ("direct connection") [0453]).
Ditty does not appear to disclose, and Gong teaches,
and a plurality of registers, the plurality of registers are in one-to-one correspondence with a plurality of hardware faults … sending, by the logic circuit, the hardware fault to a first register, wherein the first register is a register that corresponds to the hardware fault and that is in the plurality of registers (in addition to conventional PCIe device structure, additional registers ("plurality of…") are defined and correspond to various types/categories of events that a retimer may detect [0051] exemplary, a first error of a receiver link error may be detected and is recorded in particular register (930) ("a first register ... that corresponds to the hardware fault") [0051]; however, the register structure may be defined based on the structure and fields of existing interconnection protocol-defined registers [0042]);
and sending, by the first register, the hardware fault… (event register ("the first register") is read to acquire the fault details [0049])
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the error reporting and routing of Ditty to incorporate error-specific registers as disclosed by Gong. The resulting combination incorporates event registers that may be employed via a variety of extension devices [Gong; 0050], such improvements allow for a standardized mechanism to be defined by which a system software may handle fault logging, signaling, and handling on links that include extension devices which improves overall reliability, availability, and servicing of the system [Gong; 0044].
Regarding Claim 12, Ditty teaches,
The method according to claim 9, wherein the chip further comprises a first processor, and the method further comprises: sending … the hardware fault to the first processor (the L2SS safety supervisor (5014(2)) ("first processor") is directly notified of a hardware fault [0443]).
Ditty does not appear to teach and Gong teaches,
Sending, by the first register, the hardware fault… (event register ("the first register") is read to acquire the fault details [0049])
The same motivation for Claim 9 also applies to Claim 12.
Regarding Claim 14, Ditty teaches,
The method according to claim 9, wherein the chip further comprises a second processor, and the method further comprises: receiving, by the second processor, the hardware fault reported by the hardware unit (a safety watchdog (5010) detects errors or faults and reports these faults to the L1SS safety supervisor (5014(1)) ("second processor") [0425-0426]).
Regarding Claim 15, Ditty teaches,
The method according to claim 9, wherein the chip further comprises a first processor and a second processor (L1SS safety supervisor (5012(1), also called 5014(1) [0439]) ("second processor") operating on processor (5050) [0426]; L2SS safety supervisor (5014(2)) ("first processor") operating on a different processor than the L1SS safety supervisor [0439]; L1SS and L2SS are on the same SoC [0451]),
and the method further comprises: sending … the hardware fault to the first processor (the L2SS safety supervisor (5014(2)) ("first processor") is directly notified of a hardware fault [0443]);
receiving, by the second processor, the hardware fault reported by the hardware unit (a safety watchdog (5010) detects errors or faults and reports these faults to the L1SS safety supervisor (5014(1)) ("second processor") [0425-0426]);
and sending, by the first processor, the hardware fault to the off-chip processor (L3SS safety supervisor (5014(3)) ("off-chip processor") receives detected errors/failures from L2SS safety supervisor (5014(2)) ("first processor"), where (5014(3)) may be located on a different silicon ("off-chip") [0443]).
Ditty does not appear to disclose, and Gong teaches,
sending, by the first register, the hardware fault (event register ("the first register") is read to acquire the fault details [0049]).
The same motivation for Claim 9 also applies to Claim 15.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ditty et al. (U.S. PGPub No. 20190258251) in view of Boschi et al. (U.S. Patent No. 11360846).
Regarding Claim 18, Ditty teaches,
receiving a hardware fault reported by a hardware unit (errors are detected in SoC hardware (5054) ("hardware unit") [0456]; the hardware security module (5096) [Fig. 38] receives the fault [0456]);
and receiving the hardware fault reported by the hardware unit (errors are detected in SoC hardware (5054) ("hardware unit") [0456]; the hardware security module (5096) [Fig. 38] receives the fault [0456]).
Ditty does not appear to disclose, and Boschi teaches,
A troubleshooting apparatus, comprising at least one processor and a memory, wherein the at least one processor executes a program or instructions stored in the memory, to enable the troubleshooting apparatus to perform operations comprising [Col. 35, lines 34-44]:
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the non-transitory computer-readable storage medium teachings of Boschi with the method of Ditty. One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because providing an article of manufacture for implementing a method such as that of Boschi allows the benefits of the method, such as that of Ditty, to be realized.
Allowable Subject Matter
Claims 3, 5, 7, 10-11, 13, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, Ditty teaches sending, by the first processor, the hardware fault to the off-chip processor [0443]. Ditty further discloses that heartbeat monitoring is performed between L3SS (the off-chip processor) and L2SS (the first processor) [00451]. However, Ditty does not disclose, when the first processor does not receive indication information sent by the second processor, wherein the indication information represents that the second processor has received the hardware fault.
Regarding Claim 5, Ditty teaches sending, by the error management unit, the hardware fault to the first processor [0443, 0456] and sending, by the error management unit, the hardware fault to the off-chip processor [0456] sending, by the error management unit, the hardware fault to the first processor and the off- chip processor [0456]. Newly relied upon reference Volpe et al. (U.S. Patent No. 10956248) is considered to be relevant as teaching configuration registers of an IC for reporting a detected condition of the IC [Col. 18, line 56- Col. 19, line 3], however, while the registers provide reporting information such as type of notification (notification, halt, interrupt), the registers do not specify a destination for the reporting. Accordingly, the prior art of record does not disclose, [emphasis added to show distinguishable content], sending, by the error management unit, the hardware fault to the first processor when the configuration information indicates that the receive end of the hardware fault is the first processor; sending, by the error management unit, the hardware fault to the off-chip processor when the configuration information indicates that the receive end of the hardware fault is the off-chip processor; or sending, by the error management unit, the hardware fault to the first processor and the off- chip processor when the configuration information indicates that the receive end of the hardware fault comprises the first processor and the off-chip processor.
Regarding Claim 7, Ditty teaches reporting, by the second processor, the hardware fault of the hardware unit to the first processor and sending, by the error management unit, the hardware fault to the first processor [0456], also see Fig. 38, however, Ditty does not disclose, reporting, by the second processor, the hardware fault of the hardware unit to the error management unit.
Regarding Claim 10, Gong teaches a specific register for each type of error [0051], however, Gong does not disclose, [emphasis added to show distinguishable content] determining, by the logic circuit based on a number of the hardware fault, the register corresponding to the hardware fault.
Regarding Claim 11, Ditty teaches sending, by the error management unit, the hardware fault to the off-chip processor [0456]. Gong teaches the event register ("the first register") is read to acquire the fault details [0049]. Volpe (U.S. Patent No. 10956248) is considered to be relevant as teaching configuration registers of an IC for reporting a detected condition of the IC [Col. 18, line 56- Col. 19, line 3], however, while the registers provide reporting information such as type of notification (notification, halt, interrupt), the registers do not specify a destination for the reporting. Accordingly, the prior art of record does not disclose, [emphasis added to show distinguishable content], sending, by the first register, the hardware fault to the off-chip processor through the direct- connection hardware channel when the configuration information indicates that the receive end of the hardware fault is the off-chip processor.
Regarding Claim 13, Ditty teaches sending, by the error management unit, the hardware fault to the first processor [0456]. Gong teaches the event register ("the first register") is read to acquire the fault details [0049]. Volpe (U.S. Patent No. 10956248) is considered to be relevant as teaching configuration registers of an IC for reporting a detected condition of the IC [Col. 18, line 56- Col. 19, line 3], however, while the registers provide reporting information such as type of notification (notification, halt, interrupt), the registers do not specify a destination for the reporting. Accordingly, the prior art of record does not disclose, [emphasis added to show distinguishable content], sending, by the first register, the hardware fault to the first processor when the configuration information indicates that the receive end of the hardware fault is the first processor.
Regarding Claim 16, Ditty teaches sending, by the first processor, the hardware fault to the off-chip processor [0443]. Ditty further discloses that heartbeat monitoring is performed between L3SS (the off-chip processor) and L2SS (the first processor) [00451]. However, Ditty does not disclose, when the first processor does not receive indication information sent by the second processor, wherein the indication information represents that the second processor has received the hardware fault.
Regarding Claim 17, Ditty teaches that a safety watchdog (5010) detects errors or faults and reports these faults to the L1SS safety supervisor (5014(1)) ("second processor") [0425-0426] and that the logic circuit directly receives the error [0456; Fig. 38]. However, Ditty does not disclose, reporting, by the second processor, the hardware fault of the hardware unit to the logic circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Katrak (U.S. Patent No. 11500715) discloses two safety modules receiving information from a safety controller [Col. 4, lines 62-64] and a zone controller transmitting safety information to two safety controllers [Col. 5, lines 2-7], where an application processor receives the fault message [Col. 6, lines 57-59] and a fault state is asserted upon not receiving fault information by a microcontroller [Col. 12, lines 50-55].
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/A.E.W./Examiner, Art Unit 2113
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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