DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 18, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on August 13, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on November 14, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-18 are objected to because of the following informalities:
Regarding claim 1: To correct grammar (a “wherein” clause is a dependent clause that that is joined to an independent clause with a comma) and format, Examiner suggests amending the claim as follows:
Regarding claim 1: A semiconductor memory device comprising:
a memory block including dummy memory cells and normal memory cells;
a peripheral circuit configured to perform an erase operation on the memory block; and
control logic configured to control an operation of the peripheral circuit, [[;]]
wherein the control logic is configured to control, in response to an erase command for the memory block, the peripheral circuit to perform:
a first pre-program operation on first dummy memory cells connected to a first dummy word line among the dummy memory cells, by applying a first single program pulse on the first dummy word line, wherein the first dummy memory cells are simultaneously pre-programmed by the first pre-program operation;
a second pre-program operation on second dummy memory cells connected to a second dummy word line among the dummy memory cells, by applying a second single program pulse on the second dummy word line; and
an erase operation on the normal memory cells after the first pre- program operation and the second pre-program operation,[[;]]
wherein a voltage level of the first single program pulse is set based on a target threshold voltage of the first dummy memory cells and a voltage level of the second single program pulse is set based on a target threshold voltage of the second dummy memory cells.
Regarding claim 10: A method for operating a semiconductor memory device including a memory block including first dummy memory cells connected to a first dummy word line, second dummy memory cells connected to a second dummy word line, and normal memory cells connected to normal word lines, the method comprising:
receiving an erase command; and
in response to the erase command, performing:
a first pre-program operation for setting a threshold voltage of the first dummy memory cells as [at] a first target threshold voltage by applying a first single program pulse on the first dummy word line, wherein the first dummy memory cells are simultaneously pre-programmed by the first pre-program operation;
a second pre-program operation for setting a threshold voltage of the second dummy memory cells as [at] a second target threshold voltage by applying a second single program pulse on the second dummy word line; and
an erase operation on the normal memory cells after the first pre-program operation and the second pre-program operation,[[;]]
wherein the first single program pulse has a voltage level based on the first target threshold voltage, and the second single program pulse has a voltage level based on the second target threshold voltage.
11. The method of claim 10, wherein the second pre-program operation is performed after completing the first pre-program operation.
12. The method of claim 11, wherein the first dummy memory cells are located between the normal memory cells and a drain select transistor, and the second dummy memory cells are located between the normal memory cells and a source select transistor.
13. The method of claim 10, wherein, during applying the first single program pulse on the first dummy word line, a program pass voltage is applied to the second dummy word line and a plurality of normal word lines connected to the normal memory cells.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 and 10-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-7, 12, 13, and 15 of U.S. Patent No. 12,300,326. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
Regarding claim 1: Claim 1 of US 12,300,326 teaches a semiconductor memory device comprising:
a memory block including dummy memory cells and normal memory cells (see “A memory block including dummy memory cells, connected to dummy word lines, and normal memory cells, connected to normal word lines”);
a peripheral circuit configured to perform an erase operation on the memory block (see “a peripheral circuit configured to perform an erase operation on the memory block”); and
control logic configured to control an operation of the peripheral circuit;
wherein the control logic is configured to control, in response to an erase command for the memory block, the peripheral circuit to perform (see “control logic configured to control an operation of the peripheral circuit, wherein the control logic is configured to control the peripheral circuit to perform:”):
a first pre-program operation on first dummy memory cells connected to a first dummy word line among the dummy memory cells, by applying a first single program pulse on the first dummy word line, wherein the first dummy memory cells are simultaneously pre-programmed by the first pre-program operation (see “a pre-program operation on first dummy memory cells connected to a plurality of first dummy word lines among the dummy word lines, by a single pulse program using a first program pulse, in response to an erase command for the memory block, wherein the first dummy memory cells are simultaneously pro-programmed”);
a second pre-program operation on second dummy memory cells connected to a second dummy word line among the dummy memory cells, by applying a second single program pulse on the second dummy word line (see “a pre-program operation on second dummy memory cells connected to second dummy word lines among the dummy word lines, by the single pulse program pulsing a second program pulse, after the pre-program operation on the first dummy memory cells”); and
an erase operation on the normal memory cells after the first pre- program operation and the second pre-program operation (see “an erase operation on the normal memory cells” and the prefix “pre” in “a pre-program operation”, which indicates that the program operation is to performed before the erase operation.);
wherein a voltage level of the first single program pulse is set based on a target threshold voltage of the first dummy memory cells and a voltage level of the second single program pulse is set based on a target threshold voltage of the second dummy memory cells (see “wherein the control logic determines a level of the first program pulse based on a target threshold voltage of the first dummy memory cells and a level of the second program pulse based on a target threshold voltage of the second dummy memory cells”).
Regarding claim 2: Claim 1 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 3: Claim 2 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 5: Claim 5 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 6: Claim 6 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 7: Claim 7 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 4: Claim 3 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 10: Claim 12 of US 12,300,326 teaches a method for operating a semiconductor memory device including a memory block including first dummy memory cells connected to a first dummy word line, second dummy memory cells connected to a second dummy word line, and normal memory cells connected to normal word lines (see “each including first dummy memory cells, connected to a plurality of first dummy word lines, second dummy memory cells, connected to a second dummy word line, and normal memory cells, connected to normal word lines”), the method comprising:
receiving an erase command (see “receiving an erase command”);
in response to the erase command (see “corresponding to the erase command”), performing:
a first pre-program operation for setting a threshold voltage of the first dummy memory cells as [at] a first target threshold voltage by applying a first single program pulse on the first dummy word line, wherein the first dummy memory cells are simultaneously pre-programmed by the first pre-program operation (see “pre-programming first dummy memory cells included in a selected memory block, of the plurality of memory blocks, corresponding to the erase command among the plurality of memory blocks by a single pulse program using the first program pulse, wherein the first dummy memory cells included in the selected memory block are simultaneously pre-programmed”; it is inherent that such a pulse sets a threshold voltage of the dummy memory cells at a first target threshold voltage);
a second pre-program operation for setting a threshold voltage of the second dummy memory cells as [at] a second target threshold voltage by applying a second single program pulse on the second dummy word line (see “pre-programming second dummy memory cells included in the selected memory block by the single pulse program using the second program pulse after pre-programming the first dummy memory cells in the selected memory block”; it is inherent that such a pulse sets a threshold voltage of the second dummy memory cells at a second target threshold voltage); and
an erase operation on the normal memory cells after the first pre-program operation and the second pre-program operation (see “an erase operation on the normal memory cells” and the prefix “pre” in “a pre-program operation”, which indicates that the program operation is to performed before the erase operation.);
wherein the first single program pulse has a voltage level based on the first target threshold voltage, and the second single program pulse has a voltage level based on the second target threshold voltage (see “determining a level of a first program pulse based on a target threshold voltage of the first dummy memory cells” and “determining a level of a second program pulse based on a target threshold voltage of the second dummy memory cells”).
Regarding claim 11: Claim 12 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 12: Claim 15 of US 12,300,326 teaches the subject matter of this claim.
Regarding claim 13: Claim 13 of US 12,300,326 teaches the subject matter of this claim.
Allowable Subject Matter
Claims 8,9 and 14-18 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Some of these claims are also objected to above due to minor issues.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
