Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Application filed on 4/18/2025.
Claims 1-23 are pending for this examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/21/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ehtemam-Haghighi et al. (US 2016/0202673), herein referred to as Ehtemam-Haghighi ‘673.
Referring to claim 1, Ehtemam-Haghighi ‘673 teaches a method (see Abstract), comprising:
powering up a privileged core (see Fig. 3, master core 190; see Paragraph 0021, where master core periodically transitions between partial sleep and awake state) while leaving an unprivileged core unpowered (see Fig. 3, slave core 195; see Paragraph 0022, where second core remains in deep sleep state unless it receives and acknowledges a request from the first / master core), the privileged core and the unprivileged core respectively of a dual-core microcontroller (see Fig. 3, system 100 with master core 190 and slave core 195);
configuring a hardware-based mechanism of multi-core access control for the unprivileged core (see Fig. 3, shared memory 170; see Paragraphs 0049-0050, where the shared memory is used by both cores and master core needs to trigger an interrupt to wake slave core 195), the configuring at least partially based on control parameters that define access to resources of the dual-core microcontroller by the unprivileged core (see Fig. 3, shared memory 170; see Paragraphs 0049-0050, where the shared memory is used by both cores and master core needs to trigger an interrupt to wake slave core 195, i.e. waking slave core through an interrupt can be interpreted as configuring the slave core to start executing tasks); and
powering up the unprivileged core (see Paragraph 0022, where second core remains in deep sleep state unless it receives and acknowledges a request from the first / master core), operation of the unprivileged core subject to the hardware-based mechanism of access control (see Fig. 7, steps 718-722).
As to claim 2, Ehtemam-Haghighi ‘673 teaches the method of claim 1, retrieving the control parameters from a control register of a CPUIO peripheral of the dual-core microcontroller (see Fig. 3, shared memory 170; see Paragraphs 0049-0050, where both cores are storing data within shared memory that can be accessed and used by both cores depending on what is needed to execute tasks).
As to claim 4, Ehtemam-Haghighi ‘673 teaches the method of claim 1, wherein configuring the hardware-based mechanism of access control for the unprivileged core comprises: configuring a bridge between a peripheral bus and a system bus at least partially based on control parameters that define access to a peripheral connected to the system bus (see Fig. 3-4, wherein master 190 and slave 195 are communicating through interface 180, which would require a bus / bridge / interconnect to connect the two cores to allow for the transmission and reception of data signals between the cores).
As to claim 5, Ehtemam-Haghighi ‘673 teaches the method of claim 1, wherein configuring the hardware-based mechanism of access control for the unprivileged core comprises: configuring a bus matrix at least partially based on control parameters that define access to targets connected to the bus matrix by the unprivileged core (see Fig. 3-4, wherein master 190 and slave 195 are communicating through interface 180, which would require a bus / bridge / interconnect to connect the two cores to allow for the transmission and reception of data signals between the cores, where access to targets can be addresses stored in shared memory 170 needed to execute tasks, see Fig. 7).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kutch et al. (US 2022/0222117), herein referred to as Kutch ‘117 in view of Ngai (US 7,363,417), herein referred to as Ngai ‘417.
Referring to claim 9, Kutch ‘117 teaches a CPUIO peripheral (see Fig. 1, platform controller hub 130 that enables peripheral to connect to memory device 120 and processors 102, see Paragraph 0020) of a dual-core microcontroller system (see Fig. 1 system 100 with multiple processor cores 102, see Fig. 2, with cores 220-1 and 220-2), the CPUIO peripheral comprising:
a configuration and control register (see Fig. 1, register file 106; see Paragraph 0015 where register file 106 includes control registers and model specific registers) to store control parameters that define access to resources of the dual-core microcontroller system (see Paragraph 0015 where register file 106 includes control registers and model specific registers for things like how accesses are handled, multi-core configuration, sleep and wakeup controls, etc.); and
a CPUIO peripheral interface (see Fig. 6, peripheral interface 670, which is used to connect periphera1 to the processor system 600), wherein the control parameters stored at the control register are retrievable from the CPUIO peripheral interface (see Paragraph 0026, where configurations and dependencies can be shared from one computing environment to another, i.e. configuration information can be transmitted to others; see Fig. 2, where cores 220 transmit drivers to hardware devices 240).
However, Kutch ‘117 does not teach the peripheral interface specifically having a first port and control parameters stored at the control register are retrievable from the CPUIO peripheral exclusively via the first port of the CPUIO peripheral interface.
Ngai ‘417 teaches a PCIe system connecting a host with a peripheral (see Abstract; see Fig. 5, host 10, peripheral 30), where the host interface comprises a first port and second port, where a physical layer switch can be used to configure the ports such that the communication is done with a first port in a first configuration and communications is done with the second port in a second configuration (see Claim 2).
Kutch ‘117 and Ngai ‘417 apply as analogous prior arts as both pertain to the same field of endeavor of transmitting data between a host and peripheral device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kutch ‘117 system as set forth above to have the peripheral interface be a PCIe interface with multiple ports with the interface configurable to switch between modes where in a first mode the first port is used to communicate with the peripheral, as taught by Ngai ‘417, as a person of ordinary skill in the art would recognize PCIe as a well-known and used standard for peripheral interfaces for connecting peripherals to host devices, thus would be motivated to utilize a commonly used and available interface type for connecting peripheral devices and transmitting / receiving data between peripheral and host, the data which can be inclusive of configuration and control information as taught by Kutch ’117.
As to claim 10, Kutch ‘117 does not specifically teach the CPUIO peripheral of claim 9, wherein the CPUIO peripheral interface includes a second port, wherein the control parameters stored at the control register are not retrievable from the CPUIO peripheral via the second port of the CPUIO peripheral interface.
Ngai ‘417 teaches a PCIe system connecting a host with a peripheral (see Abstract; see Fig. 5, host 10, peripheral 30), where the host interface comprises a first port and second port, where a physical layer switch can be used to configure the ports such that the communication is done with a first port in a first configuration and communications is done with the second port in a second configuration (see Claim 2).
Kutch ‘117 and Ngai ‘417 apply as analogous prior arts as both pertain to the same field of endeavor of transmitting data between a host and peripheral device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kutch ‘117 system as set forth above to have the peripheral interface be a PCIe interface with multiple ports with the interface configurable to switch between modes where in a second mode the second port is used to communicate with the peripheral, as taught by Ngai ‘417, as a person of ordinary skill in the art would recognize PCIe as a well-known and used standard for peripheral interfaces for connecting peripherals to host devices, thus would be motivated to utilize a commonly used and available interface type for connecting peripheral devices and transmitting / receiving data between peripheral and host, the data which can be inclusive of configuration and control information as taught by Kutch ’117.
Referring to claim 13, Kutch ’117 teaches a system (see Fig. 1, system 100), comprising:
a first core (see Fig. 1, processor cores 107; see Fig. 2, processor core 220-1);
a second core (see Fig. 1, processor cores 107; see Fig. 2, processor core 220-2);
a bus matrix (see Fig. 1, interface buses 110);
a bus system integrated with the bus matrix (see Fig. 1, interface buses 110, which comprise of multiple buses 110, see Paragraph 0016, where buses include processor buses, PCI buses, etc.), the bus system comprising:
a first bus (see Fig. 1, buses 110; see Paragraph 0016, where buses include processor buses, PCI buses, etc.);
a second bus (see Fig. 1, buses 110; see Paragraph 0016, where buses include processor buses, PCI buses, etc.); and
a bridge to interface the first bus with the second bus (see Fig. 6, interfaces 612 and 614; see Paragraph 0065-0066, where interfaces 612 and 614 are like a north bridge and south bridge in a computer system);
a CPUIO peripheral (see Fig. 1, platform controller hub 130 that enables peripheral to connect to memory device 120 and processors 102, see Paragraph 0020); and
an access control subsystem (see Fig. 1, platform control hub 130) integrated with the first core, the bus matrix, the bus system, and the CPUIO peripheral (see Fig. 1, where platform control hub 130 is a part of processors 102 and connects to multiple peripheral devices, processor cores 107, register files 106, buses 110), the access control subsystem to manage interaction of the second core with shared resource (see Paragraph 0015 where register file 106 includes control registers and model specific registers for things like how accesses are handled, multi-core configuration, sleep and wakeup controls, etc., where a peripheral connected to a dual core / multicore system would be a shared resource to the multiple cores).
As to claim 14, Kutch ’117 teaches the system of claim 13, wherein the first core to configure one or more of the bus matrix or the access control subsystem to control access by the second core to resources, the configuring at least partially based on a control parameter of the access control subsystem (see Paragraph 0015 where register file 106 includes control registers and model specific registers for things like how accesses are handled, multi-core configuration, sleep and wakeup controls, where Examiner points out that configuring how accesses are handled would include what cores are allowed to access what resources).
As to claim 15, Kutch ’117 teaches the system of claim 14, wherein the control parameter of the access control subsystem is stored at the CPUIO peripheral, wherein the control parameter defines access to resources by the second core (see Paragraph 0015 where register file 106 includes control registers and model specific registers for things like how accesses are handled, multi-core configuration, sleep and wakeup controls, where Examiner points out that configuring how accesses are handled would include what cores are allowed to access what resources).
As to claim 16, Kutch ’117 teaches the system of claim 14, wherein the CPUIO peripheral allows access to the control parameter of the access control subsystem by the first core, and restricts access to the control parameter of the access control subsystem by the second core (see Paragraph 0015 where register file 106 includes control registers and model specific registers for things like how accesses are handled, multi-core configuration, sleep and wakeup controls, where Examiner points out that configuring how accesses are handled would include what cores are allowed to access what resources).
Allowable Subject Matter
Claims 3, 6-8, 11-12, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3, Examiner finds that prior art does not specifically teach the method of claim 2, wherein retrieving the control parameters from control registers of the CPUIO peripheral of the dual-core microcontroller comprises: accessing and reading the control parameters stored within the control registers of the CPUIO peripheral via a CPUIO interface and a port of the CPUIO interface that is dedicated to the privileged core.
As to claim 6, Examiner finds that prior art does not specifically teach the method of claim 1, wherein configuring the hardware-based mechanism of access control for the unprivileged core comprises: configuring a memory protection unit at least partially based on control parameters that define access to regions of memory by the unprivileged core.
As to claim 7, Examiner finds that prior art does not specifically teach the method of claim 1, wherein configuring the hardware-based mechanism of access control for the unprivileged core comprises: configuring a Static Random-Access Memory controller at least partially based on control parameters that define access to portions of SRAM by the unprivileged core.
As to claim 11, Examiner finds that prior art does not specifically teach the CPUIO peripheral of claim 10, comprising one or more further control registers at least some of which are accessible via the first port of the CPUIO peripheral interface and at least some of which are accessible via the second port of the CPUIO peripheral interface. Examiner notes that this in combination with the exclusively retrieving control parameters from the CPUIO peripheral exclusively via the ports of the CPUIO peripheral interface is not something specifically taught with multiple ports to the same CPUIO peripheral.
As to claim 17, Examiner finds that prior art does not specifically teach the system of claim 13, wherein respective control and status registers of the first core and the second core are within the CPUIO peripheral.
As to claim 18, Examiner finds that prior art does not specifically teach the system of claim 13, wherein control registers for hardware semaphores and Inter-Processor Interrupts are within the CPUIO peripheral.
As to claim 19, Examiner finds that prior art does not specifically teach the system of claim 13, comprising a memory protection unit, wherein the access control subsystem is further integrated with the memory protection unit.
Claims 21-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art teaches systems and methods for implementing multi-core processor systems with shared resources and requesting access control to shared resources, however, the prior art does not fairly teach or suggest, individually or in combination, a system with a first and second core, and a CPUIO peripheral coupled to both cores, where the second core requests information about assignment of resources in the multi-cores system from the first core through an inter-process communication, and the first core sends the assignment information retrieved from a set of configuration and control registers dedicated to the first core to the second core via an inter-process communication as claimed. More specifically, Examiner finds that prior art utilizes the configuration and control registers in multi-core systems in a manner where they are available to all cores to be read and used which is different from the claimed invention where there are dedicated configuration and control registers of the first core which need to have the information requested and sent to the second core from the first core as claimed. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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