DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed 07/27/2026 in response to PTO Office Action mailed 04/27/2026. The applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
In response to last Office Action, claims 1, 2, 13, 14 and 25 have been amended. No claims have been canceled. No claims have been added. As a result, claims 1-25 remain pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1-25 have been considered but are moot in view of the new ground(s) of rejection(s) due to the amendments made to the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7, 10, 13, 15-16, 19, 22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 10,854,290) and further in view of Choi (US 2025/0053337) and Sun et al. (US 2018/0373626).
As per claims 1, 13 and 25 Wu teaches a memory system (Wu: fig. 2)/a method (Wu: claim 18)/a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (Wu: col. 3, lines 11-16), comprising:
one or more memory devices; and processing circuitry coupled with the one or more memory devices (Wu: fig. 2, items 52, 40, 42) and configured to cause the memory system to:
receive a command to write a first set of data to the memory system [[and an indication of a tag associated with the first set of data]] (Wu: col. 1, lines 8-15; col. 3, lines 64-67: “The storage processing circuitry 22 receives the I/O requests from the one or more host computers”);
write, based at least in part on the command, the first set of data to a cache of the memory system in accordance with a first type of programming operation (Wu: col. 2, lines 21-29: “In some arrangements, the data written to the flash memory drive is initially saved in the SLC flash memory”; col. 5, lines 49-55: “In some arrangements, the controller 52 immediately places the new data in the SLC flash memory 40 and acknowledges successful non-volatile storage of the new data”; when DRAM cache is not present, the SLC flash memory is treated as a cache memory, because DRAM is an optional memory (fig. 2, item 54); taught as initially data is written to SLC flash memory where the data is programmed in single bit mode, e.g., a first type of programming operation); and
perform, after writing the first set of data to the cache of the memory system, a transfer operation to transfer a second set of data from the cache to a second portion of the memory system in accordance with a second type of programming operation, wherein the processing circuitry is configured to cause the memory system to maintain the first set of data in the cache after the transfer operation based at least in part on the first set of data being associated with the tag (Wu: col. 2, lines 21-29: “performing the data placement operations includes labeling data as hot data and cold data while the data is initially saved in the SLC flash memory. Once the data in the SLC flash memory is appropriately labeled, any data that is labeled as cold data in the SLC flash memory can be moved from the SLC flash memory to the MLC flash memory based on such labeling”; taught as data is labeled as hot or cold (e.g., tagged) and cold data is written to the MLC flash memory, e.g., data is written as a second type of programming operation).
Wu fails to teach the controller receives a write command with an indication of a tag with the first set of data. Choi teaches a write command with an indication of a tag with the first set of data (Choi: par. [0124]: “The controller 120 may recognize, through hint information included in a write request provided from the host 300, that the data to be written is cold data. The hint information indicates an attribute (e.g., hot/warm/cold) of the data requested to be written”). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the command with tag as taught by Choi in the system of Wu so that the controller can easily determine the type of the data and label the data accordingly and write or transfer data by initially writing data to SLC memory to provide faster write access (Wu: col. 5, lines 49-55: “Such operation provides fast write operation time to the external device 32 (i.e., SLC flash memory write speed)”) and then transferring cold data to MLC by keeping hot data in the SLC cache thereby freeing memory space in the SLC flash to provide faster write operations of new data and thus improves the performance of the memory system (Wu: col. 6, lines 8-17).
Wu and Choi teach hot and cold data, where it is readily apparent that hot data is considered as data accessed with high frequency and cold data are accessed with less frequency. However, Wu and Choi fail to teach wherein the tag indicates a first access latency. Sun teaches receiving a command to write data to the memory system and an indication of tag associated with the data which indicates a first access latency and access frequency (Sun: fig. 5; par. [0040]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the command with tag/hint/attribute which provides access frequency and access latency (e.g., high or low latency) as taught by Sun to improve the efficiency of the system by managing the data associated with high frequency (hot) and low latency data (Sun: par. [0005]).
Thus, the combination of Wu, Choi and Sun further teach perform, after writing the first set of data to the cache of the memory system, a transfer operation to transfer a second set of data from the cache to a second portion of the memory system in accordance with a second type of programming operation and based at least in part on the second set of data not being associated with the first access latency. As explained above, Wu teaches performing transfer operation for cold data, while maintaining hot data in SLC memory and Sun teaches transferring data from the first memory to second memory when first memory is full or does not have enough space (Sun: par. [0040]), where it would be readily apparent to one having ordinary skill in the art to transfer cold data or data having high latency (e.g., data not having low latency) to the second memory to improve the performance of the system by keeping low latency data in the SLC memory and transferring high latency data to slower MLC memory.
As per claims 3 and 15, Wu, Choi and Sun teach wherein, to perform the transfer operation, the processing circuitry is configured to cause the memory system to: determine, in response to a trigger associated with the transfer operation, whether the first set of data, the second set of data, or any combination thereof is associated with the tag (Wu: teaches labeling data as hot (first set of data) or cold (second set of data); and transfer the second set of data from the cache to the second portion of the memory system based at least in part on determining that the first set of data is associated with the tag (Wu: col. 6, lines 1-33: during idle time (trigger) cold data (e.g., second set of data) is moved from SLC flash to MLC flash; Choi: par. [0148]: “When the memory area MEM_AREA_1 is full and there is no more free space, the controller 120 may migrate the cold data from the first zone Z1 to the third zone Z3”).
As per claims 4 and 16, Wu, Choi and Sun teach wherein the trigger is based at least in part on a quantity of data within the cache satisfying a threshold quantity, a second command to perform the transfer operation, a latency condition, a garbage collection procedure, or any combination thereof Choi: par. [0148]: “When the memory area MEM_AREA_1 is full and there is no more free space, the controller 120 may migrate the cold data from the first zone Z1 to the third zone Z3”; full is treated threshold and a quantity of data within the cache).
As per claims 7 and 19, Wu, Choi and Sun teach wherein the cache comprises single-level memory cells, and wherein the second portion of the memory system comprises multiple-level memory cells (Wu: col. 8, lines 22-26; Choi: par. [0156]).
As per claims 10 and 22, Wu, Choi and Sun teach wherein the processing circuitry is further configured to cause the memory system to: write, to the cache, information that indicates the first set of data is associated with the tag (Wu: col. 2, lines 21-30: labeling data).
Claims 2, 8-9, 11-12, 14, 20-21 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 10,854,290), Choi (US 2025/0053337) and Sun et al. (US 2018/0373626) as applied to claims 1 and 13 above, and further in view of Aguilar et al. (US 2015/0331637).
As per claims 2 and 14, Wu and Choi teach wherein, to perform the transfer operation, the processing circuitry is configured to cause the memory system to: refrain from transferring, as part of the transfer operation, the first set of data from the cache to the second portion of the memory system based at least in part on the first set of data being associated with the tag (Wu: col. 2, lines 21-29; col. 5, lines 49-55; col. 6, lines 1-26; col. 6, lines 59-60: “Here, if all data is initially saved in the SLC flash memory 40, the hot data is maintained in the SLC flash memory 40”; Choi: par. [0148] teaches keeping hot data in SLC portion and migrates cold data to MLC portion, which means the system of Wu and Choi teach the transfer operation which refrain from transferring the first set of data tagged/labeled as hot).
Wu and Choi expressly fail to teach wherein the tag indicates a high priority level.
Choi indicates frequently accessed as hot data (Choi: col. 1, lines 36-67) and Sun teaches data with high frequency and low latency (fig. 5). Aguilar teaches that the data expected to frequently accessed is assigned to high priority (Aguilar: par. [0036]). Thus, it would be readily apparent to one having ordinary skill in the art before the effective filing date of the claimed invention to assign higher priority as taught by Aguilar so that the higher priority data is stored in SLC memory and thus improving the system performance by accessing higher priority data at a faster speed.
As per claims 8-9 and 20-21, Wu and Choi teach wherein the processing circuitry is further configured to cause the memory system to: receive, at the memory system, a second write command to write a third set of data to the memory system, [[the third set of data not associated with the tag]]; write, based at least in part on the second write command, the third set of data to the cache of the memory system in accordance with the first type of programming operation (Wu and Choi as explained with respect to claim 1 above teach initially writing data to SLC flash memory portion, which teaches the third set of data is written in accordance with the first type of programming; Wu: col. 5, lines 49-55: “In some arrangements, the controller 52 immediately places the new data in the SLC flash memory 40 and acknowledges successful non-volatile storage of the new data”).
Wu and Choi fail to teach that the third set of data is not associated with the tag. Aguilar teaches (par. [0036]) providing hinted write command indicating a priority level (e.g., data expected to be accessed frequently or hot data) and also teaches non-hinted write command which do not provide any indication. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the hinted command which designates that the write data is a hot data or high priority data and provide non-hinted data indicating data without any priority or cold data as an alternate to the hinted command which indicates either the data is hot data or cold data as an engineering decision, which provides predicted result of identifying data types and based on the type of data manage the storage of the hot or cold data.
Thus, the combination of Wu, Choi and Aguilar teach perform, after writing the third set of data to the cache of the memory system, a second transfer operation to transfer the third set of data from the cache to the second portion of the memory system in accordance with the second type of programming operation, wherein the processing circuitry is configured to cause the memory system to maintain the first set of data in the cache after the second transfer operation based at least in part on the first set of data being associated with the tag. As indicated, when the second write command with no tag indication (e.g., cold data) is received, initially data with no tag is stored in the SLC cache and then the cold data is transferred to the MLC flash memory and maintain the first set of data (hot data) in the SLC flash cache memory as taught with respect to claim 1 above.
Claims 11 and 23 are similar in scope with claims 2 and 14 above. As explained with respect to claims 2 and 14 above, Wu teaches labeling/tagging the first data is hot and Aguilar teaches hot data as high/first priority data. Thus, claims 11 and 23 are rejected under same rationales as applied to claims 2 and 14 above.
As per claims 12 and 24, Wu, Choi and Aguilar teach wherein the processing circuitry is further configured to cause the memory system to: associate, based at least in part on the transfer operation, the first set of data with a second tag corresponding to a second priority different than the first priority; and perform, after associating the first set of data with the second tag, a second transfer operation to transfer the first set of data from the cache to the second portion of the memory system in accordance with the second type of programming operation. Wu (col. 6, lines 1-45 teaches: “during idle time events, the controller 52 determines whether any data in the SLC flash memory 40 has become cold data and, if so, evicts that cold data from the SLC flash memory 40 to the MLC flash memory 42” and “during idle time events, the controller 52 determines whether any data in the MLC flash memory 42 has become hot data”, . The process of determining any data becomes cold data and transferring to data from SLC to MLC and similarly any data becoming hot, transferring from MLC to SLC indicates that the tags associated with the data during transfer operation is changed from first tag to second tag or from second tag to first tag.
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 10,854,290), Choi (US 2025/0053337) and Sun et al. (US 2018/0373626) as applied to claims 1 and 13 above, and further in view of Xu et al. (US 2023/0093218).
As per claims 5 and 17, Wu and Choi fail to teach wherein the tag is based at least in part on the first set of data being associated with an artificial intelligence model, a machine learning model, or any combination thereof.
Xu teaches storing write data of the particular application based on whether the application (thread) is latency sensitive or latency insensitive and/or application data category such as hot or cold (Xu: pars. [0141] – [0150]). Xu expressly fails to teach machine learning model application. However, according to current disclosure par. [0009] the machine learning applications are latency sensitive, therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to indicate/tag/hint the data associated with a machine learning application as a high priority data and store in the SLC cache as taught by Xu to improve the system performance by storing latency sensitive data in the SLC cache.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 10,854,290), Choi (US 2025/0053337) and Sun et al. (US 2018/0373626) as applied to claims 1 and 13 above, and further in view of Zeng et al. (US 2025/0173080).
As per claims 6 and 18, Wu and Choi fail to teach wherein the tag is based at least in part on the first set of data being associated with a virtual random access space for a host system associated with the memory system.
Zeng teaches storing host swap data to a cache of the secondary device such as NVME cache or HDD cache (Zeng: fig. 2, items 40; pars. [0003], [0004], [0007]). Zeng teaches that the swap out data is stored in the swap cache so that it can be swap in when needed, therefore storing swap out data (e.g., data associated with virtual random access space of host i.e., data swapped out of host internal memory to external storage space such as NVME or HDD (fig. 2)) in the SLC cache of NVME to improve data swapping speed by swapping out of the host memory to SLC cache and swapping in from SLC cache to host memory. Thus, it would be readily apparent to one having ordinary skill in the art to associate a tag/a hint with the data associated with the virtual random access space (swap partition) so that the data is written to SLC cache when evicted from the host memory and quickly swapped in when the needed again from the SLC cache to host memory.
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
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