Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 21 April 2025.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,3-8,14, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US PG PUB No. 2020/0341840) in view of Lo (US PG PUB No. 20200264876).
As per claim 1, a memory (see FIG 3: 70) comprising:
a first storage region configured to store therein upper data included in the host data (see Chang FIG 11: 134 Zone 1 and [0078]); and
a second storage region configured to store therein lower data included in the host data (see Chang FIG 11: 134 Zone 2 and [0078]),
wherein a refresh rate for the first storage region and a refresh rate for the second storage region are different from each other (see Chang [0039]).
However, Chang does not expressly disclose but in the same field of endeavor Lo discloses
wherein the host data includes a plurality of rational numbers each of which includes an integer part and a decimal part, the lower data including some of the decimal part, and the upper data including the integer part and the rest of the decimal part (see Lo FIG 17: 1720 and [0190]).
[Lo discloses dividing the rational number into a activation value mantissas and outlier value mantissas, where the outlier portion corresponds to other part of a divided rational number as recited in the claims (see Lo [0190]: “The shift controller 1750 configures the shifter 1755 such that the other bits of mantissa can be selected as the outlier mantissa values.”).]
It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo.
The suggestion/motivation for doing so would have been for the benefit of low and high precision format (see Lo [0224]).
Therefore it would have been obvious before the effective filing date of the invention It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo for the benefit of low and high precision format to arrive at the invention as specified in the claims.
As per claim 3, the memory of claim 1,
wherein the refresh rate for the first storage region is higher than the refresh rate for the second storage region (see Chang [0078]).
As per claim 4, the memory of claim 1,
further comprising a refresh control circuit configured to control a refresh operation on the first and second storage regions in response to a refresh command so that the respective first and second storage regions are refreshed at different refresh rates from each other (see Chang FIG 3: 132 and [0064]).
As per claim 5, the memory of claim 1,
further comprising a refresh control circuit configured to control a refresh operation to be performed on both the first storage region and the second storage region in response to a first refresh command and controlling a refresh operation to be performed on the first storage region in response to a second refresh command (see Chang FIG 3: 132 and [0064]).
As per claim 6, the memory of claim 1,
wherein the first storage region has a storage characteristic different from that of the second storage region (see Chang [0078]).
As per claim 7, the memory of claim 6,
wherein the first storage region has a flip-flop storage characteristic (see Chang [0113]).
As per claim 8, the memory of claim 6,
wherein the second storage region with a nonvolatile storage characteristic that perform a refresh operation to maintain stored data (see Chang [0035]).
As per claim 14, Chang discloses a memory system comprising:
a memory including first and second storage regions and configured to refresh the first storage region at a first rate and the second storage region at a second rate (see Chang [0068]); and
However, Chang does not expressly disclose but in the same field of endeavor Lo discloses a controller configured to:
separate a data piece into upper data and lower data in response to a write request provided together with the data pieces (see Lo FIG 17: 1745 and [0188]), and
control the memory to store the upper data and the lower data into the first and second regions, respectively (see Lo FIG 17: 1770, and 1760 and [0189]).
wherein the host data includes a plurality of rational numbers each of which includes an integer part and a decimal part, the lower data including some of the decimal part, and the upper data including the integer part and the rest of the decimal part (see Lo FIG 17: 1720 and [0190]).
[Lo discloses dividing the rational number into a activation value mantissas and outlier value mantissas, where the outlier portion corresponds to other part of a divided rational number as recited in the claims (see Lo [0190]: “The shift controller 1750 configures the shifter 1755 such that the other bits of mantissa can be selected as the outlier mantissa values.”).]
It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo.
The suggestion/motivation for doing so would have been for the benefit of low and high precision format (see Lo [0224]).
Therefore it would have been obvious before the effective filing date of the invention It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo for the benefit of low and high precision format to arrive at the invention as specified in the claims.
As per claim 15, the memory system of claim 14,
wherein the first rate is greater than the second rate (see Chang [0068]).
As per claim 18, the memory system of claim 14, wherein the controller is
further configured to:
read the first and second parts from the respective first and second storage regions in response to a read request for the data piece, and combine the read first and second parts into the data piece to be provided as a response to the read request (see Lo FIG 17 and [0189]).
As per claim 19, the memory system of claim 14,
wherein the controller is further configured to control the memory to refresh the first and second storage regions (see Chang [0068]).
Claims 9,12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prins (US PG PUB No. 2009/0172257) in view of Lo (US PG PUB No. 20200264876).
As per claim 9, a method for operating a memory system, the method comprising:
receiving, by a memory controller, a write request including host write data and a host write address from a host (see Prins FIG 5: 501);
separating, by the memory controller, the host write data into upper data and lower data (see Prins [0087]);
generating, by the memory controller, a first write address and a second write address based on the host write address (see Prins [0088]);
directing, by the memory controller, a memory to perform an operation of writing the upper data into a first storage region that is selected based on the first write address (see Prins [0104]);
storing, by the memory, the upper data into the first storage region (see Prins [105]);
directing, by the memory controller, the memory to perform an operation of writing the lower data into a second storage region that is selected based on the second write address (see Prins [0104]); and
storing, by the memory, the lower data into the second storage region (see Prins [0105]).
[Prins discloses splitting data and storing the data into different storage areas and further discloses MLC (see e.g., Prins [0651]).]
However, Prins does not expressly disclose but in the same field of endeavor Lo discloses
wherein the host data includes a plurality of rational numbers each of which includes an integer part and a decimal part, the lower data including some of the decimal part, and the upper data including the integer part and the rest of the decimal part (see Lo FIG 17: 1720 and [0190]).
[Lo discloses dividing the rational number into a activation value mantissas and outlier value mantissas, where the outlier portion corresponds to other part of a divided rational number as recited in the claims (see Lo [0190]: “The shift controller 1750 configures the shifter 1755 such that the other bits of mantissa can be selected as the outlier mantissa values.”).]
It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo.
The suggestion/motivation for doing so would have been for the benefit of low and high precision format (see Lo [0224]).
Therefore it would have been obvious before the effective filing date of the invention It would have been obvious before the effective filing date of the invention to further store a plurality of rational numbers each of which includes an integer part and decimal part as taught by Lo for the benefit of low and high precision format to arrive at the invention as specified in the claims.
As per claim 12, the method of claim 9, wherein:
the host write data include a plurality of numbers each of which is 2N bits, and the separating includes separating, from the host write data, upper N bits of each of the plurality of numbers as the upper data and lower N bits of each of the plurality of numbers as the lower data, where N is an integer greater than 0 (see Prins [0651]).
[Prins broadly discloses storing data where the data is taken as inclusive of integers and floating point data.]
As per claim 13, the method of claim 9, further comprising:
receiving, by the memory controller, a read request including a host read address from the host (see Prins FIG 4: 401 and [0113]);
generating, by the memory controller, a first read address and a second read address based on the host read address (see Prins FIG 4: 402 and [0114]);
directing, by the memory controller, the memory to perform a read operation for the first storage region that is selected based on the first read address (see Prins FIG 4: 403 and [0115]);
reading, by the memory, the upper data from the first storage region (see Prins FIG 4: 404 and [0116]);
directing, by the memory controller, the memory to perform a read operation for the second storage region that is selected based on the second read address (see Prins FIG 4: 403 and [0115]);
reading, by the memory, the lower data from the second storage region (see Prins FIG 4: 404 and [0116]);
generating, by the memory controller, host read data by combining the read upper and lower data; and providing, by the memory controller, the host with the host read data (see Prins FIG 4: 407 and [0119])
Claims 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prins (US PG PUB No. 2009/0172257) in view of Lo (US PG PUB No. 20200264876) as applied to claim 9 above and further in view of Chang (US PG PUB No. 2020/0341840).
As per claim 10, the method of claim 9, wherein further comprising
However, Prins does not expressly disclose but in the same field of endeavor Chang discloses
refreshing, by the memory, the first storage region at a first refresh rate and the second storage region at a second refresh rate, the first refresh rate being greater than the second refresh rate (see Chang [0039]).
It would have been obvious before the effective filing date of the invention to refresh regions as taught by Chang.
The suggestion/motivation for doing so would have been for the benefit of more fine grain refresh control (see Chang [0068]).
Therefore it would have been obvious before the effective filing date of the invention to further refresh the storage regions as taught by Chang for the benefit of fine grain refresh control to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1st ARGUMENT:
Lastly, for at least the foregoing reasons, any proposed combination of Chang and Prins fails to teach or suggest all of the features of independent claims 1, 9, and 14. The Office Action has thus failed to establish that independent claims 1, 9, and 14, and their respective dependent claims are prima facie obvious.
The Examiner is therefore respectfully requested to withdraw the 35 U.S.C. 102(a)(1) rejections and the 35 U.S.C. 103 rejections of claims 1, 3-10, 12-15, and 18-19, and to allow these claims.
Examiner notes Lo is relied upon to teach the argued subject matter.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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