Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 21 April 2025.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: controller in claim 14, support for which was taken as FIG 1: 110 and Paragraph [0026] of the Specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-19 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-18 of U.S. Patent No 12314578. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present application are broader than and encompass the subject matter of the claims of the patent.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US PG PUB No. 2020/0341840)
As per claim 1, a memory (see FIG 3: 70) comprising:
a first storage region configured to store therein upper data (see Chang FIG 11: 134 Zone 1 and [0078]); and
a second storage region configured to store therein lower data (see Chang FIG 11: 134 Zone 2 and [0078]),
wherein a refresh rate for the first storage region and a refresh rate for the second storage region are different from each other (see Chang [0039]).
As per claim 2, the memory of claim 1, wherein:
the upper data include more integers than the lower data, and the lower data include more decimal numbers than the upper data (see Chang [0043]).
As per claim 3, the memory of claim 1,
wherein the refresh rate for the first storage region is higher than the refresh rate for the second storage region (see Chang [0078]).
As per claim 4, the memory of claim 1,
further comprising a refresh control circuit configured to control a refresh operation on the first and second storage regions in response to a refresh command so that the respective first and second storage regions are refreshed at different refresh rates from each other (see Chang FIG 3: 132 and [0064]).
As per claim 5, the memory of claim 1,
further comprising a refresh control circuit configured to control a refresh operation to be performed on both the first storage region and the second storage region in response to a first refresh command and controlling a refresh operation to be performed on the first storage region in response to a second refresh command (see Chang FIG 3: 132 and [0064]).
As per claim 6, the memory of claim 1,
wherein the first storage region has a storage characteristic different from that of the second storage region (see Chang [0078]).
As per claim 7, the memory of claim 6,
wherein the first storage region has a flip-flop storage characteristic (see Chang [0113]).
As per claim 8, the memory of claim 6,
wherein the second storage region with a nonvolatile storage characteristic that perform a refresh operation to maintain stored data (see Chang [0035]).
Claims 9,11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Prins (US PG PUB No. 2009/0172257)
As per claim 9, a method for operating a memory system, the method comprising:
receiving, by a memory controller, a write request including host write data and a host write address from a host (see Prins FIG 5: 501);
separating, by the memory controller, the host write data into upper data and lower data (see Prins [0087]);
generating, by the memory controller, a first write address and a second write address based on the host write address (see Prins [0088]);
directing, by the memory controller, a memory to perform an operation of writing the upper data into a first storage region that is selected based on the first write address (see Prins [0104]);
storing, by the memory, the upper data into the first storage region (see Prins [105]);
directing, by the memory controller, the memory to perform an operation of writing the lower data into a second storage region that is selected based on the second write address (see Prins [0104]); and
storing, by the memory, the lower data into the second storage region (see Prins [0105]).
[Prins discloses splitting data and storing the data into different storage areas and further discloses MLC (see e.g., Prins [0651]).]
As per claim 11, the method of claim 9, wherein:
the upper data include more integers than the lower data, and the lower data include more decimal numbers than the upper data (see Prins [0651]).
[Prins broadly discloses storing data where the data is taken as inclusive of integers and floating point data.]
As per claim 12, the method of claim 9, wherein:
the host write data include a plurality of numbers each of which is 2N bits, and the separating includes separating, from the host write data, upper N bits of each of the plurality of numbers as the upper data and lower N bits of each of the plurality of numbers as the lower data, where N is an integer greater than 0 (see Prins [0651]).
[Prins broadly discloses storing data where the data is taken as inclusive of integers and floating point data.]
As per claim 13, the method of claim 9, further comprising:
receiving, by the memory controller, a read request including a host read address from the host (see Prins FIG 4: 401 and [0113]);
generating, by the memory controller, a first read address and a second read address based on the host read address (see Prins FIG 4: 402 and [0114]);
directing, by the memory controller, the memory to perform a read operation for the first storage region that is selected based on the first read address (see Prins FIG 4: 403 and [0115]);
reading, by the memory, the upper data from the first storage region (see Prins FIG 4: 404 and [0116]);
directing, by the memory controller, the memory to perform a read operation for the second storage region that is selected based on the second read address (see Prins FIG 4: 403 and [0115]);
reading, by the memory, the lower data from the second storage region (see Prins FIG 4: 404 and [0116]);
generating, by the memory controller, host read data by combining the read upper and lower data; and providing, by the memory controller, the host with the host read data (see Prins FIG 4: 407 and [0119])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prins (US PG PUB No. 2009/0172257) in view of Chang (US PG PUB No. 2020/0341840).
As per claim 10, the method of claim 9, wherein further comprising
However, Prins does not expressly disclose but in the same field of endeavor Chang discloses
refreshing, by the memory, the first storage region at a first refresh rate and the second storage region at a second refresh rate, the first refresh rate being greater than the second refresh rate (see Chang [0039]).
It would have been obvious before the effective filing date of the invention to refresh regions as taught by Chang.
The suggestion/motivation for doing so would have been for the benefit of more fine grain refresh control (see Chang [0068]).
Therefore it would have been obvious before the effective filing date of the invention to further refresh the storage regions as taught by Chang for the benefit of fine grain refresh control to arrive at the invention as specified in the claims.
Claims 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US PG PUB No. 2020/0341840) in view of Prins (US PG PUB No. 2009/0172257)
As per claim 14, a memory system comprising:
a memory including first and second storage regions and configured to refresh the first storage region at a first rate and the second storage region at a second rate (see Chang [0068]); and
However, Chang does not expressly disclose but in the same field of endeavor Trika discloses a controller configured to:
separate first and second parts from a data piece in response to a write request provided together with the data piece (see Prins [0087]);, and
control the memory to store the first and second parts into the respective first and second storage regions (see Prins [0104]);.
It would have been obvious before the effective filing date of the invention to separate first and second parts of a data piece in response to a write request
As per claim 15, the memory system of claim 14,
wherein the first rate is greater than the second rate (see Chang [0068]).
As per claim 16, the memory system of claim 14, wherein:
the data piece represents a rational number, the first part represents an integer part of the rational number, and the second part represents a decimal part of the rational number (see Prins [0651]).
[Prins broadly discloses storing data where the data is taken as inclusive of integers and floating point data.]
As per claim 17, the memory system of claim 14, wherein:
the first part is a predetermined number of upper bits within the data piece, and the second part is remaining lower bits within the data piece (see Prins [0651]: “MLC”).
As per claim 18, the memory system of claim 14, wherein the controller is
further configured to:
read the first and second parts from the respective first and second storage regions in response to a read request for the data piece (see Prins FIG 4: 404 and [0116]), and
combine the read first and second parts into the data piece to be provided as a response to the read request (see Prins FIG 4: 407 and [0119]).
As per claim 19, the memory system of claim 14,
wherein the controller is further configured to control the memory to refresh the first and second storage regions (see Chang [0068]).
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
2020/0051616 : A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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