Prosecution Insights
Last updated: August 17, 2026
Application No. 19/183,997

TOGGLING SWITCH STATE BASED ON DETECTED BEHAVIOR ASSOCIATED WITH COMPONENT

Non-Final OA §DP
Filed
Apr 21, 2025
Priority
Oct 30, 2017 — provisional 62/578,657 +3 more
Examiner
WALKER, MICHAEL JARED
Art Unit
Tech Center
Assignee
Block Inc.
OA Round
1 (Non-Final)
57%
Grant Probability
Moderate
1-2
OA Rounds
1y 4m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
162 granted / 285 resolved
-3.2% vs TC avg
Strong +32% interview lift
Without
With
+31.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
20 currently pending
Career history
310
Total Applications
across all art units

Statute-Specific Performance

§101
32.8%
-7.2% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
15.4%
-24.6% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 285 resolved cases

Office Action

§DP
DETAILED ACTION 1. Claims 1-20 are currently pending. The effective filing date of the present application is 10-30-2017. Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting 3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-10, 12-15, and 17 of U.S. Patent No. 12,299,661. Claims 1-8, 10, 14-17, and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, and 8-11 of U.S. Patent No. 11,983,688. Claims 1-6, 10, 14-17, and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-7 of U.S. Patent No. 11,257,058. Although the claims at issue are not identical, they are not patentably distinct from each other because use of synonyms and the broadening of scope. 18628864 12,299,661 11,983,688 11,257,058 1 (similarly claim 4). A system for security, the system comprising: 1 (Similarly claim 18). A system for controlling access to an interface device, the system comprising: 1. A system for controlling access to an output device between two processors, the system comprising: 1. A point of sale (POS) system with a display screen that is shared between a main processor and a secure processor without compromising tamper protection of the secure processor, the POS system comprising: a first component; a processor that communicates with the interface device through a switch while the switch is in a first state; a first processor that generates a first output and provides the first output to an output device through a switch while the switch is in a first state; the secure processor, wherein the secure processor is in the secure enclosure, wherein the main processor generates a security user interface, wherein the secure processor provides the security user interface to the display screen through the switch while the switch is in a second state; a second component; and the interface device, wherein the interface device communicates with the processor through the switch to operate a user interface using the interface device while the switch is in the first state. the output device, wherein the output device outputs the first output when the switch is in the first state, wherein the output device outputs the second output when the switch is in the second state. the display screen, wherein the display screen displays a transaction user interface provided by the main processor while the switch is in the first state, wherein the display screen displays the security user interface provided by the secure processor while the switch is in the second state. a switch, wherein one or more communications are conveyed between the first component and the second component through the switch while the switch is in a first state, wherein the switch electrically couples the first component to the second component while the switch is in the first state, wherein the switch toggles from the first state to a second state in response to a detection of a predetermined type of behavior associated with the first component, and wherein the switch electrically decouples the first component from the second component while the switch is in the second state. the switch, wherein the switch toggles from the first state to a second state in response the switch, wherein the switch is toggled between a plurality of states that includes the first state and the second state, wherein the switch electrically couples the output device to the first processor in the first state, wherein the switch electrically couples the output device to the second processor in the second state; and 8. (Currently Amended) The system of claim 1, wherein the first processor is configured to toggle the switch between the plurality of states in response to detecting an indication of at least one of unexpected network activity or unsanctioned network activity. the switch in the secure enclosure, wherein the secure processor controls setting of the switch to one of a plurality of states that includes the first state and the second state, wherein the switch electrically couples the display screen to the main processor in the first state, wherein the switch electrically couples the display screen to the secure processor in the second state; and 3. (original) The POS system of claim 1, wherein the secure processor toggles the switch from the first state to the second state in response to the tamper detection circuity detecting the attempt to tamper with the secure enclosure, wherein the security user interface indicates that the attempt to tamper has been detected. 2 (similarly claims 5 and 6). The system of claim 1, wherein the predetermined type of behavior includes a malfunction. 10. (Original) The system of claim 1, wherein the suspicious behavior is associated with a malfunction by the processor. 2. (Original) The system of claim 1, wherein the first processor is configured to toggle the switch between the plurality of states in response to detecting that the second processor is compromised. 3. (original) The POS system of claim 1, wherein the secure processor toggles the switch from the first state to the second state in response to the tamper detection circuity detecting the attempt to tamper with the secure enclosure, wherein the security user interface indicates that the attempt to tamper has been detected. 3 (similarly claim 13 and 19). The system of claim 1, wherein the predetermined type of behavior associated with the first component corresponds to an event affecting the first component. 8. (Original) The system of claim 1, further comprising: tamper detection circuitry, wherein the suspicious behavior is associated with a tamper attempt detected using the tamper detection circuitry. 3. (Original) The system of claim 1, wherein the first processor is configured to toggle the switch between the plurality of states in response to detecting, using tamper detection circuitry, an attempt to tamper with circuitry associated with the second processor. 3. (original) The POS system of claim 1, wherein the secure processor toggles the switch from the first state to the second state in response to the tamper detection circuity detecting the attempt to tamper with the secure enclosure, wherein the security user interface indicates that the attempt to tamper has been detected. 7. The method of claim 4, wherein the predetermined type of behavior is associated with network activity. 9. The system of claim 1, wherein the suspicious behavior is associated with network activity. 8. (Currently Amended) The system of claim 1, wherein the first processor is configured to toggle the switch between the plurality of states in response to detecting an indication of at least one of unexpected network activity or unsanctioned network activity. 8. The method of claim 4, wherein the predetermined type of behavior is associated with data to be received by at least one of the first component or the second component. 17. (Original) The system of claim 1, wherein the processor detects the suspicious behavior associated with the processor, wherein the processor causes the switch to toggle from the first state to the second state in response to the detection of the suspicious behavior by the processor. 5. (Currently Amended) The system of claim 1, wherein the first processor is configured to toggle the switch between the plurality of states in response to detecting that the second processor is at least one of: malfunctioning, misbehaving, or acting unusually. 9. The method of claim 4, wherein the predetermined type of behavior is associated with data to be output by at least one of the first component or the second component. 12. (Original) The system of claim 1, wherein the suspicious behavior is associated with data to be output by the processor. 10. The method of claim 4, wherein the predetermined type of behavior is associated with an event detected using tamper detection circuitry. 8. The system of claim 1, further comprising: tamper detection circuitry, wherein the suspicious behavior is associated with a tamper attempt detected using the tamper detection circuitry. 11. The system of claim 1, further comprising: a secure enclosure protected by tamper detection circuitry, wherein the secure enclosure includes at least the switch and the first processor. 3. The POS system of claim 1, wherein the secure processor toggles the switch from the first state to the second state in response to the tamper detection circuity detecting the attempt to tamper with the secure enclosure, wherein the security user interface indicates that the attempt to tamper has been detected. 11. The method of claim 4, wherein the first component is prevented from performing a specific type of operation while the switch is in the second state. 13. (Original) The system of claim 1, wherein the processor is prevented from performing a specific type of operation while the switch is in the second state. 12. The method of claim 4, wherein detecting the predetermined type of behavior associated with the first component includes detecting that the first component is performing the predetermined type of behavior. 17. (Original) The system of claim 1, wherein the processor detects the suspicious behavior associated with the processor, wherein the processor causes the switch to toggle from the first state to the second state in response to the detection of the suspicious behavior by the processor. 13. The method of claim 4, wherein detecting the predetermined type of behavior associated with the first component includes detecting an event affecting the first component. 17. (Original) The system of claim 1, wherein the processor detects the suspicious behavior associated with the processor, wherein the processor causes the switch to toggle from the first state to the second state in response to the detection of the suspicious behavior by the processor. 14. The method of claim 4, wherein a processor is included in at least one of the first component or the second component. Claim 1. a processor that communicates with the interface device through a switch while the switch is in a first state; the switch, wherein the switch toggles from the first state to a second state in response to detection of a suspicious behavior associated with the processor, Claim 1 a first processor that generates a first output and provides the first output to the output device through a switch while the switch is in a first state; a second processor that generates a second output and provides the second output to the output device through the switch while the switch is in a second state; the switch, Claim 1 wherein the main processor provides the transaction user interface to a display screen through a switch while the switch is in a first state; the secure processor, wherein the secure processor is in the secure enclosure, wherein the main processor generates a security user interface, wherein the secure processor provides the security user interface to the display screen through the switch while the switch is in a second state; 15. The method of claim 4, wherein an output device is included in at least one of the first component or the second component, wherein the output device includes at least one of a display or a speaker. 6. The system of claim 1, wherein the interface device includes at least one of a speaker, a headset, or a microphone. 9. The system of claim 1, wherein the output device includes at least one of a display, a speaker, a headset, a printer, or a network interface. 7. The system of claim 5, wherein the output device is a speaker, wherein the first output is a first sound, wherein the second output is a second sound. 6. The system of claim 5, wherein the output device is a display screen, wherein the first output is a transaction user interface, wherein the second output is a security user interface. 16. The method of claim 4, wherein an input device is included in at least one of the first component or the second component, wherein the input device includes at least one of a button, a touch-sensitive surface, a microphone, a mouse, or a transaction object reader. 5. (Original) The system of claim 1, wherein the interface device includes a touchscreen. 6. (Original) The system of claim 1, wherein the interface device includes at least one of a speaker, a headset, or a microphone. 9. (Original) The system of claim 1, wherein the output device includes at least one of a display, a speaker, a headset, a printer, or a network interface. 7. (original) The system of claim 5, wherein the output device is a speaker, wherein the first output is a first sound, wherein the second output is a second sound. 17. The method of claim 4, wherein a communication interface is included in at least one of the first component or the second component, wherein the communication interface includes at least one of a wired communication interface or a wireless communication interface. 7. The system of claim 1, wherein the interface device includes a network communication interface that communicates over a network. 10. The system of claim 1, wherein the first output and the second output include, respectively, at least one of: user interfaces, sounds, printed documents, or network data transmissions. 2. The POS system of claim 1, further comprising an audio output device, wherein the switch electrically couples the audio output device to the main processor in the first state, wherein the switch electrically couples the audio output device to the secure processor in the second state. 18. The method of claim 4, wherein a third component restricts conveyance of the one or more communications across the switch to a predetermined direction while the switch is in the first state. 14. (Original) The system of claim 1, further comprising: a diode that prevents data flow across the switch in a first direction to restrict data flow across the switch to a second direction. 20. The method of claim 4, wherein detecting the predetermined type of behavior associated with the first component includes detecting, by a third component, the predetermined type of behavior associated with the first component. 15. The system of claim 1, further comprising second processor, wherein the switch electrically couples the interface device to the second processor in the second state, wherein the switch electrically decouples the interface device from the second processor in the first state.: Claim 1 wherein the switch electrically couples the output device to the first processor in the first state, wherein the switch electrically couples the output device to the second processor in the second state; Claim1 wherein the switch electrically couples the display screen to the main processor in the first state, wherein the switch electrically couples the display screen to the secure processor in the second state Allowable Subject Matter 4. The following is a statement of reasons for the indication of allowable subject matter: The reason for allowable subject matter of claims 1-20 in the instant application is because the prior art of record fails to teach the overall combination as claimed. Therefore, it would not have been obvious to one of ordinary skill in the art to modify the prior art to meet the combination above without unequivocal hindsight and one of ordinary skill would have no reason to do so. Neither Bedier (US 2016/0117662), Hattori (US 2015/0302708), Krock (US 2008/0104631), Hayhow (US 2011/007834), nor Sullivan (US 5351296) teach a system, and method for sharing control of one component between second component using a switch and multiple states. Upon further searching the examiner could not identify any prior art to teach these limitations. The prior art on record, alone or in combination, neither anticipates, reasonably teaches, not renders obvious the Applicant' s claimed invention. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See Notice of References Cited, PTO form 892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JARED WALKER whose telephone number is (303)297-4407. The examiner can normally be reached Monday-Thursday 9:00 AM -5:00 PM CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fahd Obeid can be reached at (571)270-3324. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JARED WALKER/Primary Examiner, Art Unit 3627 Michael.walker@uspto.gov
Read full office action

Prosecution Timeline

Apr 21, 2025
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12694383
SELF-SERVICE TERMINAL (SST) MANAGEMENT ASSISTANCE
4y 10m to grant Granted Jul 28, 2026
Patent 12694304
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT
3y 5m to grant Granted Jul 28, 2026
Patent 12694408
SYSTEM AND METHOD FOR PARTIAL PAYMENT AUTHORIZATION
2y 12m to grant Granted Jul 28, 2026
Patent 12682314
METHOD FOR INBOUND INVENTORY PUTAWAY
3y 7m to grant Granted Jul 14, 2026
Patent 12675106
MULTI-SENSOR PERCEPTION FOR RESOURCE TRACKING AND QUANTIFICATION
4y 2m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
57%
Grant Probability
88%
With Interview (+31.6%)
2y 8m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 285 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month