DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 2022/0157238; hereinafter Wang), in view of Park et al (US 2021/0398490; hereinafter Park).
• Regarding claims 1 and 10, Wang discloses a display device (¶ 58), comprising:
a pixel circuit (figure 4), the pixel circuit comprising:
a light-emitting element (element OLED in figure 4),
a first resetting circuit (element T4 in figure 4 and ¶ 92),
a control circuit (elements T3 and T8 in figure 4 and ¶s 91 and 96) and
a driving circuit (element T1 in figure 4 and ¶ 89),
wherein the first resetting circuit is electrically connected to a first resetting control terminal, a first initial voltage terminal and a first node (Scan(n-1), Vint, and P, respectively, in figure 4), and configured to write a first initial voltage from the first initial voltage terminal into the first node under control of a first resetting control signal from the first resetting control terminal (¶ 92);
the control circuit is electrically connected to a first control terminal, a second control terminal, the first node, a control terminal of the driving circuit and a first terminal of the driving circuit (note the relationship between EM, P, Q, Scan(n), and elements T1, T3, and T8 in figure 4), and configured to control the control terminal of the driving circuit to be electrically connected to the first node under control of a first control signal from the first control terminal (¶ 96), and control the first node to be electrically connected to the first terminal of the driving circuit under control of a second control signal from the second control terminal (¶ 91);
the first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is configured to drive the light-emitting element to emit light (element T1 is connected to element OLED via element T6 in figure 4);
However, Wang fails to disclose the additional details of the pixel circuit.
In the same field of endeavor, Park discloses where a voltage value of the first initial voltage is larger than or equal to 5V and smaller than or equal to 8V (¶ 73; where one of ordinary skill in the art would have found it obvious to obtain a narrower range of voltages through routine optimization).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of according to the teachings of Park, for the purposes of “initializing a gate electrode of a driving transistor T1” and “initializing an anode of a light emitting element” (¶ 73).
• Regarding claims 2-9 and 11-18, Wang, in view of Park, discloses everything claimed, as applied to claim 1. Additionally, Wang discloses where:
Claims 2 & 11: the pixel circuit further comprises:
a second resetting circuit (element T9 in figure 4 and ¶ 103),
the second resetting circuit is electrically connected to a second resetting control terminal, a second initial voltage terminal and the first node (EM, Vint, and P, respectively, in figure 4), and configured to write a second initialization voltage from the second initial voltage terminal into the first node under control of a second resetting control signal from the second resetting control terminal (¶ 103; where claim 2 does not preclude the first and second initial terminals from the the same initial voltage terminal and does not preclude the first and second initialization voltages from being the same initialization voltage).
Claims 3 & 12: the pixel circuit further comprises:
an energy storage circuit (element C in figure 4 and ¶ 88),
a data written-in circuit (element T2 in figure 4 and ¶ 90),
a first light-emission control circuit (element T5 in figure 4 and ¶ 93) and
a second light-emission control circuit (element T6 in figure 4 and ¶ 94);
a first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, a second terminal of the energy storage circuit is electrically connected to a first voltage terminal, and the energy storage circuit is configured to store electric energy (note the relationship between ELVDD and elements C and T1 in figure 4 and ¶ 88);
the first light-emission control circuit is electrically connected to a light-emission control terminal, the first voltage terminal and a second terminal of the driving circuit (note the relationship between ELVDD and EM and elements T1 and T5 in figure 4), and configured to control the first voltage terminal to be electrically connected to the second terminal of the driving circuit under control of a light-emission control signal from the light-emission control terminal (¶ 93);
the second light-emission control circuit is electrically connected to the light-emission control terminal, the first terminal of the driving circuit and a first electrode of the light-emitting element (note the relationship between E< and elements OLED, T1, and T6 in figure 4), and configured to control the first terminal of the driving circuit to be electrically connected to the first electrode of the light-emitting element under control of the light-emission control signal (¶ 94);
the data written-in circuit is electrically connected to a written-in control terminal, a data line and the second terminal of the driving circuit (note the relationship between Data and elements T1 and T2 in figure 4), and configured to write a data voltage from the data line into the second terminal of the driving circuit under control of a written-in control signal from the written-in control terminal (¶ 90);
a second electrode of the light-emitting element is electrically connected to a second voltage terminal (note the relationship between ELVSS and element OLED in figure 4).
Claims 4 & 13: the pixel circuit further comprises:
a third resetting circuit (element T7 in figure 4 and ¶ 95),
the third resetting circuit is electrically connected to a third resetting control terminal, the first electrode of the light-emitting element and a third initial voltage terminal (note the relationship between Scan(n) and Vint and elements OLED and T7 in figure 4), and configured to write a third initial voltage from the third initial voltage terminal into the first electrode of the light-emitting element under control of a third resetting control signal from the third resetting control terminal (¶ 95; where claim 4 does not preclude the first, second, and third initial voltage terminals from being the same initial voltage terminal and does not preclude the first, second, and third initialization voltages from being the same initialization voltage).
Claims 5 & 14: the first resetting circuit comprises:
a first transistor (element T4 in figure 4),
a control electrode of the first transistor is electrically connected to the first resetting control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node (note the relationship between P, Scan(n-1), and Vint and element T4 in figure 4).
Claims 6 & 15: the control circuit comprises:
a second transistor (element T8 in figure 4) and
a third transistor (element T3 in figure 4);
a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit (note the relationship between EM and P and elements T1 and T8 in figure 4);
a control electrode of the third transistor is electrically connected to the second control terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the first terminal of the driving circuit (note the relationship between P and Scan(n) and elements T1 and T3 in figure 4).
Claims 7 & 16: the second resetting circuit comprises:
a fourth transistor (element T9 in figure 4),
a control electrode of the fourth transistor is electrically connected to the second resetting control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node (note the relationship between EM, P, and Vint and element T9 in figure 4).
Claims 8 & 17: the energy storage circuit comprises a storage capacitor (element C in figure 4),
the first light-emission control circuit comprises a fifth transistor (element T5 in figure 4),
the second light-emission control circuit comprises a sixth transistor (element T6 in figure 4),
the driving circuit comprises a driving transistor (element T1 in figure 4), and
the data written-in circuit comprises a seventh transistor (element T2 in figure 4);
a control electrode of the fifth transistor is electrically connected to the light-emission control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit (note the relationship between ELVDD and EM and elements T1 and T5 in figure 4);
a control electrode of the sixth transistor is electrically connected to the light-emission control terminal, a first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element (note the relationship between EM and elements OLED, T1, and T6 in figure 4);
a control electrode of the seventh transistor is electrically connected to the written-in control terminal, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit (note the relationship between Data and Scan(n) and elements T1 and T2 in figure 4);
a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal (note the relationship between ELVDD and elements C and T1 in figure 4);
a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit (element T1 in figure 4).
Claims 9 & 18: the third resetting circuit comprises:
an eighth transistor (element T7 in figure 4 and ¶ 95),
a control electrode of the eighth transistor is electrically connected to the third resetting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element (note the relationship between Scan(n) and Vint and elements OLED and T7 in figure 4).
However, Wang fails to disclose the additional details of the pixel circuit.
In the same field of endeavor, Park discloses where:
Claims 2 & 11: a voltage value of the second initial voltage is larger than or equal to −5V and smaller than or equal to −2V (¶ 73; where one of ordinary skill in the art would have found it obvious to obtain a narrower range of voltages through routine optimization).
Claims 4 & 13: a voltage value of the third initial voltage is larger than or equal to −5V and smaller than or equal to −2V (¶ 73; where one of ordinary skill in the art would have found it obvious to obtain a narrower range of voltages through routine optimization).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of according to the teachings of Park, for the purposes of “initializing a gate electrode of a driving transistor T1” and “initializing an anode of a light emitting element” (¶ 73).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 7, 9, 10, 13, 14, 8, 12, 11, 15-20, 8, 12, and 11, respectively, of U.S. Patent No 12,307,960 (resulting from parent application 18/025,952), in view of Park.
• Regarding claims 1-18, US 12,307,960 claims everything in claims 6-20 except the additional details of specific voltage values.
In the same field of endeavor, Park discloses the additional details of specific voltage values (¶ 73; where one of ordinary skill in the art would have found it obvious to obtain a narrower range of voltages through routine optimization).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 12,307,960 according to the teachings of Park, for the purposes of “initializing a gate electrode of a driving transistor T1” and “initializing an anode of a light emitting element” (¶ 73).
US 19/184,560
US 12,307,960 (18/025,952)
1. A pixel circuit, comprising
a light-emitting element,
a first resetting circuit,
a control circuit and
a driving circuit,
wherein the first resetting circuit is electrically connected to a first resetting control terminal, a first initial voltage terminal and a first node, and configured to write a first initial voltage from the first initial voltage terminal into the first node under control of a first resetting control signal from the first resetting control terminal;
the control circuit is electrically connected to a first control terminal, a second control terminal, the first node, a control terminal of the driving circuit and a first terminal of the driving circuit, and configured to control the control terminal of the driving circuit to be electrically connected to the first node under control of a first control signal from the first control terminal, and control the first node to be electrically connected to the first terminal of the driving circuit under control of a second control signal from the second control terminal;
the first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is configured to drive the light-emitting element to emit light;
wherein a voltage value of the first initial voltage is larger than or equal to 5V and smaller than or equal to 8V.
6. A pixel circuit, comprising
a light-emitting element,
a first resetting circuit,
a control circuit and
a driving circuit,
wherein the first resetting circuit is electrically connected to a first resetting control terminal, a first initial voltage terminal and a first node, and during a first resetting stage of a display period, the first resetting circuit is configured to write a first initial voltage from the first initial voltage terminal into the first node under control of a first resetting control signal from the first resetting control terminal;
the control circuit is electrically connected to a first control terminal, a second control terminal, the first node, a control terminal of the driving circuit and a first terminal of the driving circuit, and during the first resetting stage and a second resetting stage arranged one after another in the display period, the control circuit is configured to control the control terminal of the driving circuit to be electrically connected to the first node under control of a first control signal from the first control terminal, and control the first node to be electrically connected to the first terminal of the driving circuit under control of a second control signal from the second control terminal; and
the first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is configured to drive the light-emitting element to emit light.
Park: ¶ 73
2. The pixel circuit according to claim 1, further comprising
a second resetting circuit,
wherein the second resetting circuit is electrically connected to a second resetting control terminal, a second initial voltage terminal and the first node, and configured to write a second initialization voltage from the second initial voltage terminal into the first node under control of a second resetting control signal from the second resetting control terminal;
wherein a voltage value of the second initial voltage is larger than or equal to −5V and smaller than or equal to −2V.
7. The pixel circuit according to claim 6, further comprising
a second resetting circuit,
wherein the second resetting circuit is electrically connected to a second resetting control terminal, a second initial voltage terminal and the first node, and configured to write a second initialization voltage from the second initial voltage terminal into the first node under control of a second resetting control signal from the second resetting control terminal.
Park: ¶ 73
3. The pixel circuit according to claim 1, further comprising
an energy storage circuit,
a data written-in circuit,
a first light-emission control circuit and
a second light-emission control circuit;
wherein a first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, a second terminal of the energy storage circuit is electrically connected to a first voltage terminal, and the energy storage circuit is configured to store electric energy;
the first light-emission control circuit is electrically connected to a light-emission control terminal, the first voltage terminal and a second terminal of the driving circuit, and configured to control the first voltage terminal to be electrically connected to the second terminal of the driving circuit under control of a light-emission control signal from the light-emission control terminal;
the second light-emission control circuit is electrically connected to the light-emission control terminal, the first terminal of the driving circuit and a first electrode of the light-emitting element, and configured to control the first terminal of the driving circuit to be electrically connected to the first electrode of the light-emitting element under control of the light-emission control signal;
the data written-in circuit is electrically connected to a written-in control terminal, a data line and the second terminal of the driving circuit, and configured to write a data voltage from the data line into the second terminal of the driving circuit under control of a written-in control signal from the written-in control terminal; a second electrode of the light-emitting element is electrically connected to a second voltage terminal.
9. The pixel circuit according to claim 6, further comprising
an energy storage circuit,
a data written-in circuit,
a first light-emission control circuit and
a second light-emission control circuit;
wherein a first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, a second terminal of the energy storage circuit is electrically connected to a first voltage terminal, and the energy storage circuit is configured to store electric energy;
the first light-emission control circuit is electrically connected to a light-emission control terminal, the first voltage terminal and a second terminal of the driving circuit, and configured to control the first voltage terminal to be electrically connected to the second terminal of the driving circuit under control of a light-emission control signal from the light-emission control terminal;
the second light-emission control circuit is electrically connected to the light-emission control terminal, the first terminal of the driving circuit and a first electrode of the light-emitting element, and configured to control the first terminal of the driving circuit to be electrically connected to the first electrode of the light-emitting element under control of the light-emission control signal;
the data written-in circuit is electrically connected to a written-in control terminal, a data line and the second terminal of the driving circuit, and configured to write a data voltage from the data line into the second terminal of the driving circuit under control of a written-in control signal from the written-in control terminal; a second electrode of the light-emitting element is electrically connected to a second voltage terminal.
4. The pixel circuit according to claim 3, further comprising
a third resetting circuit,
wherein the third resetting circuit is electrically connected to a third resetting control terminal, the first electrode of the light-emitting element and a third initial voltage terminal, and configured to write a third initial voltage from the third initial voltage terminal into the first electrode of the light-emitting element under control of a third resetting control signal from the third resetting control terminal;
wherein a voltage value of the third initial voltage is larger than or equal to −5V and smaller than or equal to −2V.
10. The pixel circuit according to claim 9, further comprising
a third resetting circuit,
wherein the third resetting circuit is electrically connected to a third resetting control terminal, the first electrode of the light-emitting element and a third initial voltage terminal, and configured to write a third initial voltage from the third initial voltage terminal into the first electrode of the light-emitting element under control of a third resetting control signal from the third resetting control terminal.
Park: ¶ 73
5. The pixel circuit according to claim 1, wherein the first resetting circuit comprises
a first transistor, a control electrode of the first transistor is electrically connected to the first resetting control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node.
13. The pixel circuit according to claim 6, wherein the first resetting circuit comprises
a first transistor, a control electrode of the first transistor is electrically connected to the first resetting control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node.
6. The pixel circuit according to claim 1, wherein the control circuit comprises
a second transistor and
a third transistor;
a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit;
a control electrode of the third transistor is electrically connected to the second control terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.
14. The pixel circuit according to claim 6, wherein the control circuit comprises
a second transistor and
a third transistor;
a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit;
a control electrode of the third transistor is electrically connected to the second control terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.
7. The pixel circuit according to claim 2, wherein the second resetting circuit comprises
a fourth transistor,
a control electrode of the fourth transistor is electrically connected to the second resetting control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
8. The pixel circuit according to claim 7, wherein the second resetting circuit comprises
a fourth transistor,
a control electrode of the fourth transistor is electrically connected to the second resetting control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
8. The pixel circuit according to claim 3, wherein
the energy storage circuit comprises a storage capacitor,
the first light-emission control circuit comprises a fifth transistor,
the second light-emission control circuit comprises a sixth transistor,
the driving circuit comprises a driving transistor, and
the data written-in circuit comprises a seventh transistor;
a control electrode of the fifth transistor is electrically connected to the light-emission control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit;
a control electrode of the sixth transistor is electrically connected to the light-emission control terminal, a first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;
a control electrode of the seventh transistor is electrically connected to the written-in control terminal, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit;
a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;
a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit.
12. The pixel circuit according to claim 9, wherein
the energy storage circuit comprises a storage capacitor,
the first light-emission control circuit comprises a fifth transistor,
the second light-emission control circuit comprises a sixth transistor,
the driving circuit comprises a driving transistor, and
the data written-in circuit comprises a seventh transistor;
a control electrode of the fifth transistor is electrically connected to the light-emission control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit;
a control electrode of the sixth transistor is electrically connected to the light-emission control terminal, a first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;
a control electrode of the seventh transistor is electrically connected to the written-in control terminal, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit;
a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;
a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit.
9. The pixel circuit according to claim 4, wherein the third resetting circuit comprises
an eighth transistor,
a control electrode of the eighth transistor is electrically connected to the third resetting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.
11. The pixel circuit according to claim 10, wherein the third resetting circuit comprises
an eighth transistor,
a control electrode of the eighth transistor is electrically connected to the third resetting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.
10. A display device comprising
the pixel circuit according to claim 1.
15. A display device comprising
the pixel circuit according to claim 6.
11. The display device according to claim 10, further comprising
a second resetting circuit,
wherein the second resetting circuit is electrically connected to a second resetting control terminal, a second initial voltage terminal and the first node, and configured to write a second initialization voltage from the second initial voltage terminal into the first node under control of a second resetting control signal from the second resetting control terminal;
wherein a voltage value of the second initial voltage is larger than or equal to −5V and smaller than or equal to −2V.
16. The display device according to claim 15, wherein the pixel circuit further comprises
a second resetting circuit,
wherein the second resetting circuit is electrically connected to a second resetting control terminal, a second initial voltage terminal and the first node, and configured to write a second initialization voltage from the second initial voltage terminal into the first node under control of a second resetting control signal from the second resetting control terminal.
Park: ¶ 73
12. The display device according to claim 10, further comprising
an energy storage circuit,
a data written-in circuit,
a first light-emission control circuit and
a second light-emission control circuit;
wherein a first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, a second terminal of the energy storage circuit is electrically connected to a first voltage terminal, and the energy storage circuit is configured to store electric energy;
the first light-emission control circuit is electrically connected to a light-emission control terminal, the first voltage terminal and a second terminal of the driving circuit, and configured to control the first voltage terminal to be electrically connected to the second terminal of the driving circuit under control of a light-emission control signal from the light-emission control terminal;
the second light-emission control circuit is electrically connected to the light-emission control terminal, the first terminal of the driving circuit and a first electrode of the light-emitting element, and configured to control the first terminal of the driving circuit to be electrically connected to the first electrode of the light-emitting element under control of the light-emission control signal;
the data written-in circuit is electrically connected to a written-in control terminal, a data line and the second terminal of the driving circuit, and configured to write a data voltage from the data line into the second terminal of the driving circuit under control of a written-in control signal from the written-in control terminal;
a second electrode of the light-emitting element is electrically connected to a second voltage terminal.
17. The display device according to claim 15, wherein the pixel circuit further comprises
an energy storage circuit,
a data written-in circuit,
a first light-emission control circuit and
a second light-emission control circuit;
wherein a first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, a second terminal of the energy storage circuit is electrically connected to a first voltage terminal, and the energy storage circuit is configured to store electric energy;
the first light-emission control circuit is electrically connected to a light-emission control terminal, the first voltage terminal and a second terminal of the driving circuit, and configured to control the first voltage terminal to be electrically connected to the second terminal of the driving circuit under control of a light-emission control signal from the light-emission control terminal;
the second light-emission control circuit is electrically connected to the light-emission control terminal, the first terminal of the driving circuit and a first electrode of the light-emitting element, and configured to control the first terminal of the driving circuit to be electrically connected to the first electrode of the light-emitting element under control of the light-emission control signal;
the data written-in circuit is electrically connected to a written-in control terminal, a data line and the second terminal of the driving circuit, and configured to write a data voltage from the data line into the second terminal of the driving circuit under control of a written-in control signal from the written-in control terminal;
a second electrode of the light-emitting element is electrically connected to a second voltage terminal.
13. The display device according to claim 12, further comprising
a third resetting circuit,
wherein the third resetting circuit is electrically connected to a third resetting control terminal, the first electrode of the light-emitting element and a third initial voltage terminal, and configured to write a third initial voltage from the third initial voltage terminal into the first electrode of the light-emitting element under control of a third resetting control signal from the third resetting control terminal;
wherein a voltage value of the third initial voltage is larger than or equal to −5V and smaller than or equal to −2V.
18. The display device according to claim 17, wherein the pixel circuit further comprises
a third resetting circuit,
wherein the third resetting circuit is electrically connected to a third resetting control terminal, the first electrode of the light-emitting element and a third initial voltage terminal, and configured to write a third initial voltage from the third initial voltage terminal into the first electrode of the light-emitting element under control of a third resetting control signal from the third resetting control terminal.
Park: ¶ 73
14. The display device according to claim 10, wherein the first resetting circuit comprises
a first transistor,
a control electrode of the first transistor is electrically connected to the first resetting control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node.
19. The display device according to claim 15, wherein the first resetting circuit comprises
a first transistor,
a control electrode of the first transistor is electrically connected to the first resetting control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node.
15. The display device according to claim 10, wherein the control circuit comprises
a second transistor and
a third transistor;
a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit;
a control electrode of the third transistor is electrically connected to the second control terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.
20. The display device according to claim 15, wherein the control circuit comprises
a second transistor and
a third transistor;
a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit;
a control electrode of the third transistor is electrically connected to the second control terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.
16. The display device according to claim 11, wherein the second resetting circuit comprises
a fourth transistor,
a control electrode of the fourth transistor is electrically connected to the second resetting control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
8. The pixel circuit according to claim 7, wherein the second resetting circuit comprises
a fourth transistor,
a control electrode of the fourth transistor is electrically connected to the second resetting control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
17. The display device according to claim 12, wherein
the energy storage circuit comprises a storage capacitor,
the first light-emission control circuit comprises a fifth transistor,
the second light-emission control circuit comprises a sixth transistor,
the driving circuit comprises a driving transistor, and
the data written-in circuit comprises a seventh transistor;
a control electrode of the fifth transistor is electrically connected to the light-emission control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit;
a control electrode of the sixth transistor is electrically connected to the light-emission control terminal, a first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;
a control electrode of the seventh transistor is electrically connected to the written-in control terminal, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit;
a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;
a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit.
12. The pixel circuit according to claim 9, wherein
the energy storage circuit comprises a storage capacitor,
the first light-emission control circuit comprises a fifth transistor,
the second light-emission control circuit comprises a sixth transistor,
the driving circuit comprises a driving transistor, and
the data written-in circuit comprises a seventh transistor;
a control electrode of the fifth transistor is electrically connected to the light-emission control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit;
a control electrode of the sixth transistor is electrically connected to the light-emission control terminal, a first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;
a control electrode of the seventh transistor is electrically connected to the written-in control terminal, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit;
a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;
a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit.
18. The display device according to claim 13, wherein the third resetting circuit comprises
an eighth transistor,
a control electrode of the eighth transistor is electrically connected to the third resetting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.
11. The pixel circuit according to claim 10, wherein the third resetting circuit comprises
an eighth transistor,
a control electrode of the eighth transistor is electrically connected to the third resetting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Zhang et al (US 2020/0286432) disclose a pixel circuit in which initialization and reset voltages in the range of approximately -1V to -5V are applied thereto (see at least ¶ 107).
b. Tian (US 2024/0021142) discloses a pixel in which a reset voltage vinit1 of -3V and an adjustment voltage vref of 4V are applied thereto (see at least ¶ 120).
Closing Remarks/Comments
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622