Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References:
Reznik (US 20220300384) – Enhanced Fencing Scheme for Cluster Systems Without Inherent Hardware Fencing, relates to claimed first virtual host system, second virtual host system.
Non-patent Literature (attached) – Yi Ren, et al, Shared-Memory Optimizations for Inter-Virtual-Machine Communication, ACM Computing Surveys (CSUR), Vol 48, Issue 4, Article No.: 49, Pages 1-42; relevant to claimed first virtual host system, second virtual host system.
Allowable Subject Matter
Claims 10, 11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
For Claims 10-11, the prior art discloses and/or renders obvious the limitations from Claims 1. The prior art does not appear to disclose the limitations from Claims 10-11 when viewed in combination with their respective base claims.
For Claim 20, the prior art discloses and/or renders obvious the limitations from Claim 12. The prior art does not appear to disclose the limitations from Claims 20 when viewed in combination with their respective base claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitations “system”, “components configured to… copy… copy” (Claim 1) have been evaluated under the three-prong test set forth in MPEP § 2181, subsection I, but the result is inconclusive. Thus, it is unclear whether this limitation should be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because these limitations are software functions without recitation of structure/hardware to perform these functions. The boundaries of this claim limitation are ambiguous; therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
In response to this rejection, applicant must clarify whether this limitation should be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Mere assertion regarding applicant’s intent to invoke or not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph is insufficient. Applicant may:
(a) Amend the claim to clearly invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, by reciting “means” or a generic placeholder for means, or by reciting “step.” The “means,” generic placeholder, or “step” must be modified by functional language, and must not be modified by sufficient structure, material, or acts for performing the claimed function;
(b) Present a sufficient showing that 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, should apply because the claim limitation recites a function to be performed and does not recite sufficient structure, material, or acts to perform that function;
(c) Amend the claim to clearly avoid invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, by deleting the function or by reciting sufficient structure, material or acts to perform the recited function; or
(d) Present a sufficient showing that 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, does not apply because the limitation does not recite a function or does recite a function along with sufficient structure, material or acts to perform that function.
Claims 2-11 are rejected based on dependency from Claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,4,12,14,21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220137864 A1) and in view of Colbert (US 20100023565 A1)
Claim 1., Lee discloses comprising:
one or more components configured to:
copy, by a first virtual host system, a set of data from a first memory copy location to a shared memory location, wherein the first memory copy location is a memory location associated with the first virtual host system (eg., 0169 Fig. 18 - [0169] In the case where the target data TD are stored in an internal memory (i.e., the first virtual memory vMEM1) of the first host 401, the target data TD may be moved from the first virtual memory vMEM1 to the first expanded virtual memory vMEM1_ex, and then, a target data transfer operation may be performed.; 0179 - memory device 512 of the memory expander 510 may not include a memory region associated with a first virtual memory and a second virtual memory and may only include the shared memory sMEM); and
copy, by one or more second virtual host systems, the set of data from the shared memory location to one or more second memory copy locations associated with the one or more second virtual host systems (eg., 0167 - the memory expander 410 may copy or transmit the target data TD; 0173 - move the target data TD, which are stored in the memory expander 210 or are referenced at the memory expander 210, to an internal memory of the second host 202; 0180 - target data TD copied to the shared memory sMEM may be directly copied from the shared memory sMEM to the second virtual memory vMEM2 through the CXL interface).
Lee does not disclose, but Colbert discloses
an emulation system (eg., 0007 - emulate the corresponding physical components )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, providing the benefit of All of the virtual hardware components of the VM may be implemented in software using known techniques (see Colbert, 0007) a virtualized computer system and, in particular, to a method and system for using swap space for host physical memory with separate swap files corresponding to different virtual machines (0003).
Claim 2. Lee discloses
wherein the one or more components are further configured to load, by the one or more second virtual host systems, the set of data from the one or more second memory copy locations (eg., 0074 - second switch SW2 may generate the IP communication packet PC_IP based on the CXL communication packet PC_CXL and may transmit the IP communication packet PC_IP to the second virtual machine VM2.).
Claim 4. Lee discloses
wherein the one or more components are further configured to store, by the first virtual host system, the set of data to the first memory copy location (eg., 0059 - the target data may be data that are generated or managed by the first virtual machine VM1. The target data may be stored in the first virtual memory vMEM1.),
wherein the one or more components, to store the set of data to the first memory copy location, are configured to store the set of data to a first portion of a cache (eg., 0120 - copy the target data TD stored in the first virtual switch memory vMEM_SW1 to the shared memory sMEM in response to the (1−b)-th CXL communication packet PC_CXL1b ([2-2]). ),
wherein the one or more components, to copy the set of data from the first memory copy location to the shared memory location, are configured to copy the set of data from the first portion of the cache to a second portion of the cache (eg., 0136 - first virtual machine VM1 may use the first virtual memory vMEM1 and the first expanded virtual memory vMEM1_ex as a virtual memory. That is, the first virtual machine VM1 may recognize and manage a region of the first virtual memory vMEM1 and a region of the first expanded virtual memory vMEM1_ex as a memory region allocated to the first virtual machine VM1.),
wherein the one or more components, to copy the set of data from the shared memory location to the one or more second memory copy locations, are configured to copy the set of data from the second portion of the cache to a third portion of the cache (eg., 0149 Fig. 14B - the first transfer operation in operation S431 may indicate an operation for transferring the target data TD from the first expanded virtual memory vMEM Lex to the first virtual switch memory vMEM_SW1,), and
wherein the one or more components, to load the set of data from the one or more second memory copy locations, are configured to load the set of data from the third portion of the cache to a central processing unit of the one or more second virtual host systems (eg., 0149 second transfer operation in operation S441 may indicate an operation for transferring the target data TD from the first virtual switch memory vMEM_SW1 to the second virtual switch memory vMEM_SW2. In an embodiment, each of the first transfer operation and the second transfer operation may be performed based on at least one of the copy operation).
Claim 12. Lee discloses A method (eg., 0047 Fig. 2 - a server system 100 ) comprising:
storing, by a first virtual host system of an emulated environment, a set of data to a first memory copy location of the emulated environment that is associated with the first virtual host system (eg., 0059 - the target data may be data that are generated or managed by the first virtual machine VM1. The target data may be stored in the first virtual memory vMEM1.);
copying, by the first virtual host system, the set of data from the first memory copy location to a shared memory location of the (eg., 0169 Fig. 18 - [0169] In the case where the target data TD are stored in an internal memory (i.e., the first virtual memory vMEM1) of the first host 401, the target data TD may be moved from the first virtual memory vMEM1 to the first expanded virtual memory vMEM1_ex, and then, a target data transfer operation may be performed.; 0179 - memory device 512 of the memory expander 510 may not include a memory region associated with a first virtual memory and a second virtual memory and may only include the shared memory sMEM); and
copying, by a second virtual host system of the the set of data from the shared memory location to a second memory copy location of the that is associated with the second virtual host system (eg., 0167 - the memory expander 410 may copy or transmit the target data TD; 0173 - move the target data TD, which are stored in the memory expander 210 or are referenced at the memory expander 210, to an internal memory of the second host 202; 0180 - target data TD copied to the shared memory sMEM may be directly copied from the shared memory sMEM to the second virtual memory vMEM2 through the CXL interface).
loading, by the second virtual host system, the set of data from the second memory copy location (eg., 0074 - second switch SW2 may generate the IP communication packet PC_IP based on the CXL communication packet PC_CXL and may transmit the IP communication packet PC_IP to the second virtual machine VM2.).
Lee does not disclose, but Colbert discloses
emulated environment, (eg., 0007 - emulate the corresponding physical components )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, providing the benefit of All of the virtual hardware components of the VM may be implemented in software using known techniques (see Colbert, 0007) a virtualized computer system and, in particular, to a method and system for using swap space for host physical memory with separate swap files corresponding to different virtual machines (0003).
Claim 14 is rejected for reasons similar to Claim 4 above.
Claim 21. Lee discloses A compute express link (CXL) (eg., 0007 - compute express link (CXL) protocol-based communication; 0047 Fig. 2 - a server system 100)
one or more components configured to: store, by a first virtual CXL compliant host, a set of data to a first local memory location associated with the first virtual CXL compliant host (eg., 0059 - the target data may be data that are generated or managed by the first virtual machine VM1. The target data may be stored in the first virtual memory vMEM1.);
copy, by the first virtual CXL compliant host, the set of data from the first local memory location to a shared direct-access memory location (eg., 0169 Fig. 18 - [0169] In the case where the target data TD are stored in an internal memory (i.e., the first virtual memory vMEM1) of the first host 401, the target data TD may be moved from the first virtual memory vMEM1 to the first expanded virtual memory vMEM1_ex, and then, a target data transfer operation may be performed.; 0179 - memory device 512 of the memory expander 510 may not include a memory region associated with a first virtual memory and a second virtual memory and may only include the shared memory sMEM); and
copy, by a second virtual CXL compliant host, the set of data from the shared direct-access memory location to a second local memory location associated with the second virtual CXL compliant host (eg., 0167 - the memory expander 410 may copy or transmit the target data TD; 0173 - move the target data TD, which are stored in the memory expander 210 or are referenced at the memory expander 210, to an internal memory of the second host 202; 0180 - target data TD copied to the shared memory sMEM may be directly copied from the shared memory sMEM to the second virtual memory vMEM2 through the CXL interface).
load, by the second virtual CXL compliant host, the set of data from the second local memory location (eg., 0074 - second switch SW2 may generate the IP communication packet PC_IP based on the CXL communication packet PC_CXL and may transmit the IP communication packet PC_IP to the second virtual machine VM2.).
Lee does not disclose, but Colbert discloses
compliant memory system emulator (eg., 0007 - emulate the corresponding physical components; 0011 - 0011] Some interface is generally required between the guest software within a VM and the various hardware components and devices in the underlying hardware platform. This interface--which may be referred to generally as "virtualization software" )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, providing the benefit of All of the virtual hardware components of the VM may be implemented in software using known techniques (see Colbert, 0007) a virtualized computer system and, in particular, to a method and system for using swap space for host physical memory with separate swap files corresponding to different virtual machines (0003).
Claims 3, 9, 13, 19, 22, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220137864 A1) and in view of Colbert (US 20100023565 A1) and further in view of Smits (US 20080270709 )
Claim 3. Lee in view of Colbert does not disclose, but Smits discloses
wherein the one or more components are further configured to determine that one or more software coherency primitives associated with the emulation system include errors based on comparing the set of data loaded from the one or more second memory copy locations with the set of data stored to the first memory copy location wherein the software coherency primitives are associated with an application that produces correct results when implemented across a hardware coherent memory cluster (eg., [0033] The data that has been copied to the shared memory is checked to determine if the data is coherent or if it was corrupted before it was retrieved (block 413). For example, the session data may have been corrupted by whatever issue caused the virtual machine to fail. If the data is corrupt, then the data is discarded and an error is generated ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Smits, providing the benefit of copying shared data from a virtual machine to a shared closure on demand. This process improves system efficiency by avoiding the copying of data in the large number of cases where the same virtual machine is the next to request access and use of the data. Load balancing and failure recovery are supported by copying the data to the shared closure when the data is requested by another virtual machine or recovering the data from the failed virtual machine and storing it in the shared closure (see Smits).
Claim 9. Lee in view of Colbert does not disclose, but Smits discloses
wherein the first virtual host system and the one or more second virtual host systems are associated with a first physical device, and wherein the shared memory location is associated with a second physical device different from the first physical device (eg.,0040 Fig. 6 - server machine 611 may also support other components in addition to the server 605,… shared memory 615).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Smits, providing the benefit of copying shared data from a virtual machine to a shared closure on demand. This process improves system efficiency by avoiding the copying of data in the large number of cases where the same virtual machine is the next to request access and use of the data. Load balancing and failure recovery are supported by copying the data to the shared closure when the data is requested by another virtual machine or recovering the data from the failed virtual machine and storing it in the shared closure (see Smits).
Claim 13 is rejected for reasons similar to Claim 3 above.
Claim 19 is rejected for reasons similar to Claim 9 above.
Claim 22 is rejected for reasons similar to Claim 3 above.
Claim 25 is rejected for reasons similar to Claim 9 above.
Claims 5-7, 15-17, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220137864 A1) and in view of Colbert (US 20100023565 A1) and further in view of Hodigere (US 20250335226 )
Claim 5. Lee in view of Colbert does not disclose, but Hodigere discloses
wherein the one or more components are further configured to: memory map, by the first virtual host system, the first memory copy location to a memory address (eg., 0030 Fig. 2A - migration daemon 240 takes control of a local memory map 242 from hypervisor 225 and remaps the logical addresses used to store source memory of the guest VM 201 (“VM source memory 244”); and
memory map, by the one or more second virtual host systems, the one or more second memory copy locations to the memory address (eg., 0034 - e, updates the memory map 226 on the host 218 to map the logical addresses of the designated system memory 232 to the shared physical memory region 234).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Hodigere, providing the benefit of it is common to migrate one or all VMs hosted by the physical server node to other (e.g., better-performing) server node(s). Migration is performed without notifying the end customer and often while customer workloads are running (see Hodigere, 0001).
Claim 6. Lee in view of Colbert does not disclose, but Hodigere discloses
wherein the one or more components are further configured to memory map, by the first virtual host system and the one or more second virtual host systems, the shared memory location to a memory address (eg., [0028] The designated system memory 232 is characterized by a set of logical addresses that are mapped, in memory map 226, to a set of physical addresses. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Hodigere, providing the benefit of it is common to migrate one or all VMs hosted by the physical server node to other (e.g., better-performing) server node(s). Migration is performed without notifying the end customer and often while customer workloads are running (see Hodigere, 0001).
Claim 7. Lee in view of Colbert does not disclose, but Hodigere discloses
wherein the one or more components, to copy the set of data from the first memory copy location to the shared memory location, are configured to use a fence operation to store the set of data to the first memory copy location prior to copying the set of data from the first memory copy location to the shared memory location (eg., 0044 - utilize a garbage collection fencing key to block and prevent garbage collectors from collecting or removing B-tree keys that are deemed as garbage by the garbage collector in a file system performing a cross-region replication.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Hodigere, providing the benefit of it is common to migrate one or all VMs hosted by the physical server node to other (e.g., better-performing) server node(s). Migration is performed without notifying the end customer and often while customer workloads are running (see Hodigere, 0001).
Claim 15 is rejected for reasons similar to Claim 5 above.
Claim 16 is rejected for reasons similar to Claim 6 above.
Claim 17 is rejected for reasons similar to Claim 7 above.
Claim 23. Lee in view of Colbert does not disclose, but Hodigere discloses
wherein the one or more components are further configured to: memory map, by the first virtual CXL compliant host, the first local memory location to a first memory address (eg., 0030 Fig. 2A - migration daemon 240 takes control of a local memory map 242 from hypervisor 225 and remaps the logical addresses used to store source memory of the guest VM 201 (“VM source memory 244”); and
memory map, by the second virtual CXL compliant host, the second local memory location to the first memory address (eg., 0034 - e, updates the memory map 226 on the host 218 to map the logical addresses of the designated system memory 232 to the shared physical memory region 234);
memory map, by the first virtual CXL compliant host and the second CXL compliant host, the shared direct-access memory location to a second memory address (eg., [0028] The designated system memory 232 is characterized by a set of logical addresses that are mapped, in memory map 226, to a set of physical addresses. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Hodigere, providing the benefit of it is common to migrate one or all VMs hosted by the physical server node to other (e.g., better-performing) server node(s). Migration is performed without notifying the end customer and often while customer workloads are running (see Hodigere, 0001).
Claims 8, 18, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220137864 A1) and in view of Colbert (US 20100023565 A1) and further in view of Cooper (US 20150370586)
Claim 8. Lee in view of Colbert does not disclose, but Cooper discloses
wherein the first virtual host system, the one or more second virtual host systems, and the shared memory location are associated with a same physical device (eg., 0022 Fig. 1 - Architecture 100 includes a compute platform 102 coupled to a network interface 104 that may be integrated on the compute platform (e.g., as a network interface controller (NIC)) or otherwise operatively coupled to the compute platform (e.g., as a PCIe (Peripheral Component Interconnect Express) card installed in a PCIe expansion slot). Compute platform 102 includes a host operating system (OS) 106 running in OS memory 107 that is configured to host multiple applications running in an application memory space 108, which are depicted above host OS 106. This includes a virtual switch 109 and a hypervisor 110 that is configured to host N virtual machines 112, as depicted by virtual machines labeled VM 1, VM2 and VMN. The software components further include an SDN controller 114.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the shared memory to transfer target data from one host to a second host as disclosed by Lee, with Colbert, with Cooper, providing the benefit of virtualization approach, container-based OS virtualization is used that employs virtualized “containers” without use of a VMM or hypervisor. Instead of hosting separate instances of operating systems on respective VMs, container-based OS virtualization shares a single OS kernel across multiple containers, with separate instances of system and software libraries for each container. As with VMs, there are also virtual resources allocated to each container (see Cooper, 0004).
Claim 18 is rejected for reasons similar to Claim 8 above.
Claim 24 is rejected for reasons similar to Claim 8 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135