DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 19/184,701 has a total of 20 preliminary amended claims pending in the application; there are 3 independent claims and 17 dependent claims, which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 12-31 are rejected on the ground of nonstatutory double patenting over the claims of 1-28 of U.S. Pat. No. 12,282,683, since the claims, if allowed, would improperly extend the “right to exclude” already granted in patents. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patents and application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 12-17, 20-25 and 28-31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YUN et al. (US pub. # 2020/0050363), hereinafter, “YUN”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 12, 20 and 28, YUN discloses a storage device (data storage device 910 of fig. 9, as discloses in paragraph 0105) comprising: a non-volatile storage medium comprising a first storage node (first NVM device 910-1) and a second storage node (second NVM device 910-2), wherein the first storage node is to store a first replica of a data object (DAT1 of fig. 7) stored on the non-volatile storage medium, and wherein the second storage node is to store a second replica of the data object (DAT2 of fig. 7) [see paragraph 0105, which discloses “the management module 310 may store data the same as the write data WDAT received from the host 200 at different physical addresses, i.e., a first physical address and a second physical address according to the opcode 42 and a duplicate/split flag 47 (see FIGS. 8A and 8B) in a multi-write command (N-Write command). In some embodiments, the opcode 42 and duplicate/split flag 47 may be part of the same field. As shown in FIG. 9, the first physical address may be on a first NVM device (e.g., NAND/PRAM 910-1), and the second physical address may be on a second NVM device (e.g., NAND/PRAM 910-2). As the same write data WDAT is stored at different physical addresses of a data storage device (e.g., SSD) 910, duplication or mirroring of the write data WDAT may be carried out” and paragraph 0107, which discloses “FIG. 10 is a diagram for explaining a multi-write operation of a data processing system according to other embodiments of the inventive concept. The management module 310 may divide the write data WDAT received from the host 200 into at least two segments DAT1′ and DAT2′ according to the opcode 42 and duplicate/split flag 47 in a multi-write command (N-Write command) and may store the segments DAT1′ and DAT2′ at different physical addresses, i.e., a first physical address and a second physical addresses, respectively (in operations S120 and S130). As shown in FIG. 10, the first physical address may be on a first NVM device (e.g., NAND/PRAM 1010-1), and the second physical address may be on a second NVM device (e.g., NAND/PRAM 1010-2) of a data storage device (e.g., SSD 1010). For example, a duplicate/split flag 47 may indicate that a first part of data associated with the multi-access command should be written to a first memory device of the data storage device and not a second memory device of the data storage device, and a second part of the data associated with the multi-access command should be written to the second memory device and not the first memory device. The first segment DAT1′ may be the first half of the write data WDAT and the second segment DAT2′ may be the second half of the write data WDAT”]; and processing circuitry to: receive, from a host computing device (host 200), a compute (see fig. 11, showing DAT1 and DAT2 being added) offload command (N-Read command, as discloses in paragraph 0113) for processing the data object (see paragraph 0113); and based at least in part on receiving the compute offload command from the host computing device, perform at least one compute operation on the data object stored on the non-volatile storage medium by concurrently performing the at least one compute operation on a first portion of the first replica and on a second portion of the second replica [see paragraph 0113, which discloses “when the first and second physical addresses PBA1 and PBA2 are included in the address list Add_list of the N-Read command, the management module 310 may generate and send a first read command NVM_Read including the first physical address PBA1 to the first NVM device in operation S220 and may generate and send a second read command NVM_Read including the second physical address PBA2 to the second NVM device in operation S240. The first and second NVM devices may be the NVM devices, e.g., 410-1 and 410-2, respectively, connected to different channels, e.g., CHA and CHB, respectively, as shown in FIG. 2. Accordingly, operations S220 and S240 may be performed in parallel (e.g., at the same time)” and paragraph 0116, which discloses “the read data RDAT transmitted to the host 200 may be a combination of the first and second data DAT1 and DAT2. For instance, when the write data WDAT received from the host 200 has been divided into the first and second data DAT1 and DAT2 and separately stored at the first and second physical addresses PBA1 and PBA2 according to an N-Write command and a duplicate/split flag indicating splitting of data, the host 200 may set the opcode 42 in the N-Read command to a particular value before sending the N-Read command to the data storage device 300. The data storage device 300 may read the first and second data DAT1 and DAT2 from the first and second physical addresses PBA1 and PBA2, respectively, and send the read data RDAT obtained by combining the first and second data DAT1 and DAT2 to the host 200 according to the N-Read command in operation S260”], wherein the first portion and the second portion are different (see paragraph 0099 or 0105, disclosing different physical addresses for respective NVMs).
3. As per claims 13, 21 and 29, YUN discloses “The storage device of Claim 12” [See rejection to claim 12 above], wherein the first portion of the first replica corresponds to a different portion of the data object stored on the non-volatile storage medium than the second portion of the second replica (see paragraph 0099 or 0105, disclosing different physical addresses for respective NVMs).
4. As per claims 14, 22 and 30, YUN discloses wherein the processing circuitry is to concurrently perform the at least one compute operation on the first portion of the first replica and the second portion of the second replica by: performing the at least one compute operation on the first portion of the first replica; reading the second portion of the second replica from the second storage node; performing the at least one compute operation on the second portion of the second replica; and computing, based on performing the at least one compute operation on the first portion of the first replica and the second portion of the second replica, an output data object (see paragraphs 0113 and 0116).
5. As per claims 15, 23 and 31, YUN discloses wherein the processing circuitry is further to return the output data object as an output of the compute offload command (see paragraphs 0113 and 0116).
6. As per claims 16 and 24, YUN discloses wherein the data object comprises image data, wherein the image data is partitioned in a plurality of chunks, and wherein the plurality of chunks is padded such that a respective portion of the image data is aligned within boundaries of a corresponding chunk of the plurality of chunks (see paragraphs 0093, 0141 and fig. 8).
7. As per claims 17 and 25, YUN discloses wherein the processing circuitry is to perform the at least one compute operation by performing a visual compute task on the image data (see paragraph 0092).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 18, 19, 26 and 27 are rejected under 35 U.S.C. 103(a) as being unpatentable over YUN et al. (US pub. # 2020/0050363), hereinafter, “YUN”, in view of LU et al. (US pub. # 2012/0218942), hereinafter, “LU”.
10. As per claims 18 and 26, YUN discloses “The storage device of Claim 12” [See rejection to claim 12 above], but fails to expressly discloses wherein the processing circuitry is to perform the at least one compute operation by performing a cyclic redundancy check (CRC) verification on the data object.
Berman discloses wherein the processing circuitry is to perform the at least one compute operation by performing a cyclic redundancy check (CRC) verification on the data object (see paragraph 0152).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate LU’s teaching of a method of point-to-point characteristic of transmission in a wireless network to perform flattening processing on existing protocol stacks, into YUN’s teaching of a method for increasing transmission efficiency between a host and the data storage device, for the ability/benefit of having a data packet transmitted between an access network and a terminal through an air interface without carrying an unnecessary high layer protocol stack header.
11. As per claims 19 and 27, YUN discloses “The storage device of Claim 12” [See rejection to claim 12 above], but fails to expressly discloses wherein the non-volatile storage medium comprises a third storage node, and wherein the processing circuitry is further to: perform the at least one compute operation by performing a write operation to write the data object; identify a plurality of input/output (I/O) features associated with the write operation, wherein the plurality of I/O features is to indicate a timestamp, a type of data, and an application name; predict a lifetime of the data object based at least in part on a machine learning model, wherein the machine learning model is trained to predict the lifetime of the data object based on the plurality of I/O features; based at least in part on the lifetime of the data object, select the third storage node for storing the data object; and write the data object to the third storage node.
Berman discloses wherein the non-volatile storage medium comprises a third storage node, and wherein the processing circuitry is further to: perform the at least one compute operation by performing a write operation to write the data object; identify a plurality of input/output (I/O) features associated with the write operation, wherein the plurality of I/O features is to indicate a timestamp, a type of data, and an application name; predict a lifetime of the data object based at least in part on a machine learning model, wherein the machine learning model is trained to predict the lifetime of the data object based on the plurality of I/O features; based at least in part on the lifetime of the data object, select the third storage node for storing the data object; and write the data object to the third storage node (see paragraphs 0131 and 0134).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate LU’s teaching of a method of point-to-point characteristic of transmission in a wireless network to perform flattening processing on existing protocol stacks, into YUN’s teaching of a method for increasing transmission efficiency between a host and the data storage device, for the ability/benefit of having a data packet transmitted between an access network and a terminal through an air interface without carrying an unnecessary high layer protocol stack header.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 12-31 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights