Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202410481623.9, filed on 04/22/2024.
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 04/22/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over VIANELLO et al. (Pub. No.: US 2021/0035638) in view of Holzmann et al. (Pat. No.: US 6,301,161).
Regarding claims 1, 9 and 17, VIANELLO discloses a multi-level programming method for a memory, wherein the memory comprises a plurality of memory cells arranged in an array, and the multi-level programming method comprises:
reading a stored value of a memory cell of the memory (Fig.6, Fig.7 and [0093]-[0099]: the programmed resistance R of a memory cell is read and compared with resistance thresholds R1-R4 using resistance comparator 600);
determining whether the stored value of the memory cell is within a reference range (Fig.7 and [0105]: In an operation 705, the programmed resistance R of each of the programmed cells is for example compared with the resistance thresholds R1 and R4 of the state n, or only the threshold R4 in the case of the state 0, or only the threshold R1 in the case of the highest resistive state);
if not, applying a first adjustment signal to the memory cell to adjust the stored value of the memory cell to the reference range (Fig.7 and [0105]: If the resistance R of any cell is lower than R1 or higher than R4, then that cell has not reached the target range associated with the state n. In such a case, a new attempt is for example made to bring that cell to the target range of state n. For example, this involves applying a reset pulse in an operation 706 to reset the cell to state 7, and then repeating operations 704 and 705. In some embodiments, a limit is set on the number of times the loop formed of operations 704, 705 and 706 is executed for a given cell. For example, once a certain limit, such as one hundred attempts, has been reached, the cell is deemed faulty, and no longer used);
determining whether the stored value of the memory cell is within a target range (Fig.7 and [0107]: In operation 707, it is determined whether the resistance R of each programmed cell falls within the resistance range of the state n, in other words whether it is equal to or greater than R2 and equal to or less than R3, or in the case of state 0, just less than or equal to R3, or in the case of the highest resistive state (the state 7 in the example of FIG. 3), just equal to or greater than R2); and
if not, applying a second adjustment signal to the memory cell to adjust the stored value of the memory cell to the target range (Fig.7 and [0107]-[0112]: If not, a fine resistance control sequence is for example applied to each cell not falling within this range. This sequence is for example similar to the method of FIG. 4, except that the starting point of the resistance of each memory cell will already be relatively close to the resistance range of the targeted state, and therefore the sequence will be relatively rapid. Furthermore, in some embodiments, the fine resistance control sequence involves applying a voltage V_ICC pulse at the level determined in operation 703 for the state n, while the voltage V_P is adjusted in order to increase or decrease the programmed resistance of the concerned cells); and
wherein a minimum value of the reference range is less than or equal to a minimum value of the target range, a maximum value of the reference range is greater than or equal to a maximum value of the target range (Fig.5 and [0087]-[0089]: R1<R2 and R4>R3, such that claimed reference range R1-R4 encompasses the claimed target range R2-R3).
However, VIANELLO does not specifically teach a single-time adjustment amplitude corresponding to the second adjustment signal is less than a single-time adjustment amplitude corresponding to the first adjustment signal.
Holzmann teaches a single-time adjustment amplitude corresponding to the second adjustment signal is less than a single-time adjustment amplitude corresponding to the first adjustment signal (Fig.1, Fig.3, Fig.5 and col.3, lines 41-55: The program circuit 110 generates programming pulses to the memory cell 120 during programming. The program circuit 110 generates coarse and fine pulses having coarse and fine amplitudes, respectively, using comparison results provided by the comparator 140, wherein the fine amplitude is less than the coarse amplitude. Coarse and fine amplitudes may correspond to voltage step size, current magnitude, or programming time magnitude).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Programming Flash Memory Analog Storage Using Coarse-and-fine Sequence, as taught by Holzmann into circuit and method for programming resistive memory cells of VIANELLO, in order to provide relatively large coarse adjustments for approaching the desired programmed value and smaller fine adjustments for more accurately reaching the desired target value.
Allowable Subject Matter
Claims 2-8, 10-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 identifies the distinct features “wherein before determining whether the stored value of the memory cell is within the reference range, the multi-level programming method further comprises: presetting the target range and the reference range; and presetting control parameters of the first adjustment signal, wherein the memory cells are correspondingly connected to bit lines, word lines, and source lines, and the control parameters of the first adjustment signal comprise a bit line coarse adjustment voltage, a word line coarse adjustment voltage, and a maximum number of coarse adjustments", which are not taught or suggested by the prior art of records.
Claims 3 and 4, which respectively depend on objected-to claim 2, are allowable for at least the same reasons as claim 2.
Claim 5 identifies the distinct features “wherein before determining whether the stored value of the memory cell is within the target range, the multi-level programming method further comprises: presetting control parameters of the second adjustment signal, and wherein the memory cells are correspondingly connected to bit lines, word lines, and source lines, and the control parameters of the second adjustment signal comprise a bit line start adjustment voltage, a bit line end adjustment voltage, a bit line voltage increment step, a word line start adjustment voltage, a word line end adjustment voltage, a word line voltage increment step, a source line start adjustment voltage, a source line end adjustment voltage, a source line voltage increment step, and a maximum number of fine adjustments", which are not taught or suggested by the prior art of records.
Claims 6-8, which respectively depend on objected-to claim 5, are allowable for at least the same reasons as claim 5.
Claim 10 identifies the distinct features “wherein before determining whether the stored value is within the reference range, the control circuit is further configured to: preset the target range and the reference range; and preset control parameters of the first adjustment signal, and wherein the memory cells are correspondingly connected to the bit lines, the word lines, and the source lines, and the control parameters of the first adjustment signal comprises a bit line coarse adjustment voltage, a word line coarse adjustment voltage, and a maximum number of coarse adjustments", which are not taught or suggested by the prior art of records.
Claims 11 and 12, which respectively depend on objected-to claim 10, are allowable for at least the same reasons as claim 10.
Claim 13 identifies the distinct features “wherein before determining whether the stored value of the memory cell is within the target range, the control circuit is further configured to: preset control parameters of the second adjustment signal, and wherein the memory cells are correspondingly connected to the bit lines, the word lines, and the source lines, and the control parameters of the second adjustment signal comprise a bit line start adjustment voltage, a bit line end adjustment voltage, a bit line voltage increment step, a word line start adjustment voltage, a word line end adjustment voltage, a word line voltage increment step, a source line start adjustment voltage, a source line end adjustment voltage, a source line voltage increment step, and a maximum number of fine adjustments", which are not taught or suggested by the prior art of records.
Claims 14-16, which respectively depend on objected-to claim 13, are allowable for at least the same reasons as claim 13.
Claim 18 identifies the distinct features “wherein before determining whether the stored value is within the reference range, the control circuit is further configured to: preset the target range and the reference range; and preset control parameters of the first adjustment signal, and wherein the memory cells are correspondingly connected to the bit lines, the word lines, and the source lines, and the control parameters of the first adjustment signal comprises a bit line coarse adjustment voltage, a word line coarse adjustment voltage, and a maximum number of coarse adjustments", which are not taught or suggested by the prior art of records.
Claims 19 and 20, which respectively depend on objected-to claim 18, are allowable for at least the same reasons as claim 18.
Claims 2-8, 10-16 and 18-20 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Conclusion
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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