DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 21, 2025 and May 18, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings have been considered and accepted by the examiner.
Specification
The title, abstract, and specification have been considered and accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PGPub 2009/0240897 to Kajigaya.
Regarding claim 1, Kajigaya discloses a memory system, comprising:
a first bank group communicatively connected to a first internal bus, wherein the first internal bus is configured to communicatively connect to a first input/out (IO) (see fig. 1 and paragraphs 44-48, a memory bank MB1 is connected by lines to a route switching circuit through to one of four input/output ports A,B,C, and D);
a second bank group communicatively connected to a second internal bus (see fig. 1 and paragraph 44-48, a second memory bank MB2 is connected by its own lines to the route switching circuit);
a channel selection device configured to selectively communicatively connect the second internal bus to the first IO in a first operation mode or a second IO in a second operation mode in response to the memory system receiving a mode register write command configured to cause the memory system to operate in the first operation mode or the second operation mode (see fig. 2 and paragraph 21 and 57, the route switching circuit can connect different memory banks to different IO ports based on a control signal from an external circuit).
Regarding claim 11, Kajigaya discloses a method for operating a memory system, comprising:
receiving a mode register write command configured to cause the memory system to operate in a first operation mode or second operation mode (see paragraph 57, a control signal for setting a route is input as a command from an external circuit); and
selectively communicatively connecting a second internal bus to a first input/output in the first operation mode or a second IO in the second operation mode in response to the memory system receiving the mode register write command configured to cause the memory system to operate in the first operation mode or the second operation mode (see fig. 2 and paragraph 21 and 57, the route switching circuit can connect different memory banks to different IO ports based on a control signal from an external circuit), wherein the memory system comprises a first bank group communicatively connected to a first internal bus and a second bank group communicatively connected to a second internal bus (see fig. 1 and paragraphs 44-48, a memory bank MB1 and a second memory bank MB2 are connected by their own lines to the route switching circuit), and wherein the first internal bus is configured to communicatively connect to a first IO (see fig. 1 and paragraphs 44-48, a memory bank MB1 is connected by lines to a route switching circuit through to one of four input/output ports A,B,C, and D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kajigaya in view of US 7,221,617 to Flach et al. (“Flach”).
As applied in the rejections above, Kajigaya discloses a memory system and method for selectively connecting memory bank groups to IO ports. Kajigaya does not disclose a prefetch memory associated with a first bank group. Flach discloses a memory system wherein a memory bank group has a connected prefetch register (see fig. 1 and col. 7, lines 12-31 of Flach). It would have been obvious at the time the application was filed for the first bank group of Kajigaya to include a prefetch register of Flach in order to improve access time by enabling prefetching of data bits.
Allowable Subject Matter
Claims 2-9 and 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose or suggest the first IO includes a first channel data bus and the second IO includes a second channel data bus, wherein the first internal data bus having a larger bit width than the first channel data bus, and the second internal data bus having a same bit width as the first internal data bus.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D TSUI whose telephone number is (571)270-3253. The examiner can normally be reached Monday-Friday 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D TSUI/ Primary Examiner, Art Unit 2132
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