CTNF 19/185,014 CTNF 90564 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-4 and 6-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-30 of U.S. Patent No. 12282432 . Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below . U.S. Patent No. 12282432 1. A method of operating a computation engine, the method comprising: storing instructions in a memory; operating the memory as an associative memory, wherein the instructions are identified by nodes of a graph; and performing the instructions by the computation engine: executing a first instruction of the instructions that is identified by a first node; based on the first node branching to one or more nodes, selecting a single next branch node from among the one or more nodes based on the graph; and executing a second instruction of the instructions identified by the single next branch node. 1. A method of operating a computation engine, the method comprising: storing instructions in a memory; operating the memory as an associative memory, wherein the memory comprises a content addressable memory (CAM) and wherein the instructions are identified by nodes of a tree of a memory graph; and performing the instructions by the computation engine: executing a first instruction of the instructions that is identified by a first node; based on the first node comprising a branch to multiple nodes and based on the memory graph identifying a second node of the multiple nodes as a next branch node, selecting the second node of the multiple nodes as the next branch node; based on the first node comprising the branch to multiple nodes and the memory graph identifying a third node of the multiple nodes as the next branch node, selecting the third node of the multiple nodes as the next branch node; and executing a second instruction of the instructions identified by the next branch node . 08-36 AIA Claim s 5 and 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-30 of U.S. Patent No. 12282432 (i.e. Parent) in view of Hong (US 20160299991 A1). Parent teaches the claims of the current application as shown in the example claims in the table above but does not explicitly disclose “wherein the graph comprises a directed graph”. Hong teaches “wherein the graph comprises a directed graph” ([Hong 0122, Fig. 12] If the corresponding graph is a directed graph and there is an edge from node ‘2’ to another node, then node array 1210 would include an entry that points to an entry in neighbor array 1220.) . Parent and Hong are analogous art because they are from the same field of endeavor in graph memory. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Parent and Hong before him or her to modify the memory graph of Parent to include the directed graph of Hong, thereafter the memory graph is connected to directed graph. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory graph have more alternative in memory graph representations as suggested by Hong. It is known to combine to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Parent with Hong to obtain the invention as specified in the instant application claims. A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804 Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-9 and 11-15 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Hong (US 20160299991 A1) . Referring to claims 1 and 11, taking claim 1 as exemplary, Hong teaches A method of operating a computation engine, the method comprising: storing instructions in a memory; ([Hong abstract, 0029, 0037-0038, Fig. 1] In-memory graph analytic engine 110 performs one or more graph analytic operations on a “graph instance” that is loaded from graph database 120 and stored in-memory of one or more computing devices (or nodes). A graph instance is an in-memory version of a graph whose nodes and edges are stored in graph database 120. in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors.) operating the memory as an associative memory, wherein the instructions are identified by nodes of a graph; ([Hong 0024, 0031, Fig. 13] Techniques for efficiently creating an in-memory representation of a graph are provided. Creating an in-memory representation of a graph involves multiple phases, some of which may be performed in parallel, and may include a node loading phase, a node merging phase, a node property construction phase, an edge loading phase, an edge merging phase, and an edge property construction phase. Graph database 120 may be a relational database or an object database. For example, one node table in graph database 120 may include a row for each node in a graph. (Graph database 120 may store a different node table for each graph represented in the graph data.) Each column in the node table may correspond to a different attribute or property of the node, such as a name, an age, and a date, depending on the type of object the nodes represent.) and performing the instructions by the computation engine: executing a first instruction of the instructions that is identified by a first node; ([Hong abstract, 0029, 0037-0039, Fig. 1] In-memory graph analytic engine 110 performs one or more graph analytic operations on a “graph instance” that is loaded from graph database 120 and stored in-memory of one or more computing devices (or nodes). A graph instance is an in-memory version of a graph whose nodes and edges are stored in graph database 120. in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors. Each client connects to in-memory graph analytic engine 110 and requests certain types of tasks, such as loading a graph into memory and performing graph analytic operations, including returning information about a graph, adding nodes and edges to a graph, deleting nodes and edges from a graph, and updating properties or attributes of nodes/edges of a graph. Thus, in-memory graph analytic engine 110 translates client requests into graph operations that a storage device that stores graph database 120 recognizes or is configured to process.) based on the first node branching to one or more nodes, selecting a single next branch node from among the one or more nodes based on the graph; ([Hong 0096, Fig. 9] In the edge (i.e. branch) loading phase, graph analytic engine 110 loads edge data of a graph from graph database 120 into memory. The edge loading phase may be similar to the node loading phase described previously. The edge data may be stored in P partitions in graph database. Graph analytic engine 110 may use K threads over K connections with graph database 120. If K=P, then each thread handles a single edge list/partition. If P>K, then a single thread may create multiple edge lists/partitions in memory. Because the edge loading phase may be handled by multiple threads executing concurrently, the edge loading phase may be performed in parallel.) and executing a second instruction of the instructions identified by the single next branch node ([Hong 0096-0101, Fig. 9] FIG. 9 is a block diagram that depicts an example result 900 of an edge loading phase, in an embodiment. Result 900 includes edge lists 910-930. Edge list 910 includes edges 912 and 914, edge list 920 includes edges 922 and 924, and edge list 930 includes a single edge 932. Each edge list may originate from different partitions in graph database 120.) . With regards to claim 11, Hong further teaches computation engine is to execute the instructions by traversal of the nodes of the tree ([Hong abstract, 0029, 0037-0039, Fig. 1] In-memory graph analytic engine 110 performs one or more graph analytic operations on a “graph instance” that is loaded from graph database 120 and stored in-memory of one or more computing devices (or nodes). A graph instance is an in-memory version of a graph whose nodes and edges (i.e. tree) are stored in graph database 120. in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors. Each client connects to in-memory graph analytic engine 110 and requests certain types of tasks, such as loading a graph into memory and performing graph analytic operations, including returning information about a graph, adding nodes and edges to a graph, deleting nodes and edges from a graph, and updating properties or attributes of nodes/edges of a graph. Thus, in-memory graph analytic engine 110 translates client requests into graph operations that a storage device that stores graph database 120 recognizes or is configured to process.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claims 2 and 12, taking claim 2 as exemplary, Hong teaches The method of claim 1 further comprising: accessing the instructions from the memory independent of a program pointer input to the memory ([Hong 0038] in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors. Even though FIG. 1 depicts a single element for in-memory graph analytic engine 110, in-memory graph analytic engine 110 may be implemented on a single computing device or on multiple computing devices connected via a communication network.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claims 3 and 13, taking claim 3 as exemplary, Hong teaches The method of claim 1 wherein: the computation engine is to operate as at least one of: a Turing machine, a Turing-equivalent machine, or a Turing-complete machine ([Hong 0004, 0037-0039, 0131] In-memory graph analytic engine 110 may be implemented in hardware, software, or any combination of hardware and software. For example, in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors. In-memory graph analytic engine 110 performs one or more graph analytic operations on a “graph instance” that is loaded from graph database 120 and stored in-memory of one or more computing devices (or nodes). A graph instance is an in-memory version of a graph whose nodes and edges are stored in graph database 120. Even though FIG. 1 depicts a single element for in-memory graph analytic engine 110, in-memory graph analytic engine 110 may be implemented on a single computing device or on multiple computing devices connected via a communication network. Main memory 1406 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 1404. Such instructions, when stored in non-transitory storage media accessible to processor 1404, render computer system 1400 into a special-purpose machine that is customized to perform the operations specified in the instructions.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claims 4 and 14, taking claim 4 as exemplary, Hong teaches The method of claim 1 wherein: the computation engine comprises a processor ([Hong 0038] . For example, in-memory graph analytic engine 110 may execute on one or more nodes, each comprising one or more processors and memory (such as random access memory (RAM)) that stores instructions that are executed by the one or more processors.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claims 5 and 15, taking claim 5 as exemplary, Hong teaches The method of claim 1 wherein the graph comprises a directed graph ([Hong 0122, Fig. 12] If the corresponding graph is a directed graph and there is an edge from node ‘2’ to another node, then node array 1210 would include an entry that points to an entry in neighbor array 1220.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claim 6, Hong teaches The method of claim 1 further comprising: accessing at least one of the instructions from the memory using a search key ([Hong abstract, 0024, 0052] In one embodiment, graph database 120 stores graph data of a graph in sorted order. For example, a node table may list each node in a graph (with one or more corresponding properties), where the node table is ordered based on one or more order criteria, such as node ID. The node table may also be indexed. Additionally, the node table may be partitioned into multiple partitions that are separately indexed and/or searchable.) . Referring to claim 7, Hong teaches The method of claim 1 further comprising: storing the instructions in the associative memory; and associating a given instruction in the associative memory with a state identifier, wherein: the given instruction comprises at least one of a next state identifier, an action, or a test ([Hong abstract, 0024, 0052, 0083-0084, Fig. 6] During the node loading phase, a plurality of node ID lists are retrieved from persistent storage. Each node ID list is ordered based on one or more order criteria, such as node ID, and is read into (e.g., volatile) memory. During the node merging phase, a particular node ID is selected from among the plurality of node ID lists based on the one or more order criteria. The particular node ID is removed from its node ID list and added to a mapping that maps node IDs to node index values that indicate a location within a node array of an in-memory representation of a graph. At block 680, the next node entry from the same node ID list as the selected node entry is inserted into the priority queue (and removed from that node ID list). Block 680 may also involve incrementing a local index value for the node ID list indicating that another node entry from that node ID list has been inserted into the priority queue.) . Referring to claim 8, Hong teaches The method of claim 1 further comprising: associating, in the memory, a state identifier with an edge value for each edge of a given state ([Hong 0024, Fig. 9, 10A-10B, 11A-11G] Creating an in-memory representation of a graph involves multiple phases, some of which may be performed in parallel, and may include a node loading phase, a node merging phase, a node property construction phase, an edge loading phase, an edge merging phase, and an edge property construction phase. The mapping is used to help construct a neighbor array that stores, for each entry in the neighbor array, destination node information regarding a different edge in the graph. FIGS. 10A-10B are flow diagrams that depict a process 1000 for creating a new list of edge IDs from multiple of edge lists, in an embodiment. Process 1000 is described in context of FIGS. 11A-11G, which depict different example intermediate results of process 1000 relative to edge lists 910-930 depicted in FIG. 9.) . Referring to claim 9, Hong teaches The method of claim 1 further comprising: generating a search key to traverse the memory and locate a next state; and the search key is based on a concatenation of a current state identifier with an edge value ([Hong 0024, 0102-0103, 0111-0113, Fig. 10A] The particular node ID is removed from its node ID list and added to a mapping that maps node IDs to node index values that indicate a location within a node array of an in-memory representation of a graph. The mapping is used to help construct a neighbor array that stores, for each entry in the neighbor array, destination node information regarding a different edge in the graph. In the edge merging phase, the edge loading results (e.g., depicted in FIG. 9) are merged into a new list or array, similar to neighbor array 220. The source ID of each edge indicated in each edge list is used to edge in a graph is assigned a new index or key value that indicates a position in the new list. For example, a node index of ‘0’ indicates that the corresponding node is located at the first position in the new list. A node index of ‘10’ indicates that the corresponding node is located at the 11.sup.th position in the new list. In an embodiment, the original node IDs (as they existed in graph database 120) are still preserved.) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20160299991 A1) as applied to claim 1 above, and further in view of Wu (US 20140310302 A1) . Referring to claim 10, Hong teaches The method of claim 1 ([see above]) . Hong does not explicitly disclose further comprising: receiving an input data; performing a computational operation on the input data to create a computed value; and generating a search key from at least a portion of the computed value. Wu teaches further comprising: receiving an input data; performing a computational operation on the input data to create a computed value; and generating a search key from at least a portion of the computed value ([Wu abstract, 0020, 0046-0047, 0054-0056] A key is generated based on the graph statement. The key may be generated based on concatenating hash values that are generated based on the plurality of values. The key-value store stores the key. instead of including the values of a graph statement directly in a key, a hash value is first created for each graph value. For example, given the example graph statement above (i.e., "John" "is a father of" "Mary"), a hash value is generated for "John", a hash value is generated for "is a father of", and a hash value is generated for "Mary." (If the graph values are URIs, then a hash value is generated for each URI.)) . Hong and Wu are analogous art because they are from the same field of endeavor in graph memory. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hong and Wu before him or her to modify the memory graph of Hong to include the graph query optimizer of Wu, thereafter the memory graph is connected to graph query optimizer. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory graph have more alternative plans to optimize execution plan as suggested by Wu. It is known to combine to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Hong with Wu to obtain the invention as specified in the instant application claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132 Application/Control Number: 19/185,014 Page 2 Art Unit: 2132 Application/Control Number: 19/185,014 Page 3 Art Unit: 2132 Application/Control Number: 19/185,014 Page 4 Art Unit: 2132 Application/Control Number: 19/185,014 Page 5 Art Unit: 2132 Application/Control Number: 19/185,014 Page 6 Art Unit: 2132 Application/Control Number: 19/185,014 Page 7 Art Unit: 2132 Application/Control Number: 19/185,014 Page 9 Art Unit: 2132 Application/Control Number: 19/185,014 Page 10 Art Unit: 2132 Application/Control Number: 19/185,014 Page 11 Art Unit: 2132 Application/Control Number: 19/185,014 Page 12 Art Unit: 2132 Application/Control Number: 19/185,014 Page 13 Art Unit: 2132 Application/Control Number: 19/185,014 Page 14 Art Unit: 2132 Application/Control Number: 19/185,014 Page 15 Art Unit: 2132 Application/Control Number: 19/185,014 Page 16 Art Unit: 2132
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