Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 04/21/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figures 1-3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, i.e. including a first resistor element arranged between a first connecting region of a semiconductor substrate of a control chip and a first capacitor connected to a first terminal of the control chip.
The disclosure is objected to because of the following informalities:
In paragraph [0002], the quotation that begins with “a resistance component connected to a power supply terminal P1” is not closed by a closing quotation mark before the phrase “and paragraph 0036 describes”, because of a typographical error;
in paragraph [0034], “a maximum rated of the control chip 100” appears that it should read as “a maximum rated voltage of the control chip 100”;
in paragraph [0034], “The maximum rated is a maximum voltage” appears that it should read as “The maximum rated voltage is a maximum voltage”;
in paragraph [0035], “break down occurs” appears that it should read as “breakdown occurs”;
in paragraph [0040], “A contact region 35 and a source region 34” appears that it should read as “The contact region 35 and the source region 34”, as the contact region 35 and the source region 34 are previously recited in the preceding sentence of paragraph [0040];
in paragraph [0046], “an emitter region, the contact region 14” appears that it should read as “an emitter region, and the contact region 14”, because of a grammatical error (missing conjunction);
in paragraph [0047], “any of terminals of the control chip 100” appears that it should read as “any of the terminals of the control chip 100”;
in paragraph [0053], “the cathode region 52 of the element 40” appears that it should read as “the cathode region 42 of the element 40”, because of a typographical error, as the cathode region 52 is a region of the element 50;
in paragraph [0067], “greater than or equal to 10 Ω or less than or equal to 100 Ω” appears that it should read as “greater than or equal to 10 Ω and less than or equal to 100 Ω”, because of a typographical error, as the corresponding range is recited as greater than or equal to 10 Ω and less than or equal to 100 Ω in paragraph [0061];
in paragraph [0070], “break down occurs similarly” appears that it should read as “breakdown occurs similarly”. Appropriate correction is required.
Claim Objections
Claims 2, 8, 14, and 15 are objected to because of the following informalities:
Regarding claim 2, in lines 6-7, “a capacity value” appears that it should read as “a capacitance value”, because of a terminology error, as the value of a capacitor expressed in µF is a capacitance.
Regarding claim 8, in lines 2-3, “connected between the first resistor element and the first terminal” appears that it should read as “connected to a wiring between the first resistor element and the first terminal”, because the second capacitor 135 is connected to the wiring between the first resistor element 121 and the first terminal 101 as described in paragraph [0060] of the specification, rather than in series between the first resistor element and the first terminal; in line 3, “a capacity value” appears that it should read as “a capacitance value”, because of a terminology error, as the value of a capacitor expressed in nF is a capacitance.
Regarding claim 14, in line 2, “the power supply electric power” appears that it should read as “power supply electric power”, because of a lack of antecedent basis, as power supply electric power is not previously recited in claim 2.
Regarding claim 15, in lines 2-3, “connected between the first resistor element and the first terminal” appears that it should read as “connected to a wiring between the first resistor element and the first terminal”, because the second capacitor 135 is connected to the wiring between the first resistor element 121 and the first terminal 101 as described in paragraph [0060] of the specification, rather than in series between the first resistor element and the first terminal; in line 3, “a capacity value” appears that it should read as “a capacitance value”, because of a terminology error, as the value of a capacitor expressed in nF is a capacitance.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama (US Patent Application Publication US 2023/0421066 A1) in view of Kapre et al. (US Patent Application Publication US 2005/0286295 A1, hereinafter “Kapre”).
Regarding claim 1, Maruyama discloses (see Fig. 1) a switched-mode power supply (switching power source 200) comprising: a main transformer (transformer T1) (see [0017] of Maruyama “The switching power source 200 in the present example is provided with a primary side circuit 210, a secondary side circuit 220, and a transformer T1.”; see [0019] of Maruyama “The primary side circuit 210 has a control circuit 100, a primary side winding n1 of the transformer T1, a reset winding n3 of the transformer T1, a diode D1, and the switching element Q1.”); a switching device (switching element Q1) which performs switching control of a main current flowing through the main transformer (principal current flowing through the primary side winding n1) (see [0021] of Maruyama “The switching element Q1 is connected in series to the primary side winding n1, and is configured to perform switching control on whether a principal current is caused to flow through the primary side winding n1.”); a control chip (control circuit 100) which includes a first terminal (power source terminal VCC) and controls the switching device (see [0021] of Maruyama “The control circuit 100 is, for example, an integrated circuit chip.”; see [0021] of Maruyama “The control circuit 100 is configured to control the ON state and the OFF state of the switching element Q1.”; see [0024] of Maruyama “The primary side circuit 210 may have a power source circuit 230 configured to supply the source power to a power source terminal VCC of the control circuit 100.”); and a first capacitor (capacitor C8) connected to the first terminal of the control chip (see [0025] of Maruyama “The capacitors C8 and C9 are charged with the current having passed through the diode D5.”; see [0025] of Maruyama “Electrical power accumulated in the capacitors C8 and C9 is supplied as the source power of the control circuit 100.”), wherein the first terminal is a power supply terminal to which power supply electric power is supplied (the power source terminal VCC to which the source power is supplied from the power source circuit 230) (see [0024] of Maruyama “The primary side circuit 210 may have a power source circuit 230 configured to supply the source power to a power source terminal VCC of the control circuit 100.”).
Maruyama does not disclose a first resistor element connected to the first terminal, wherein the control chip includes a semiconductor substrate including a first connecting region connected to the first terminal, the first resistor element is arranged between the first connecting region and the first capacitor.
However, Kapre teaches (see Fig. 1a) a first resistor element (resistor RL) connected to the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) (see [0010] of Kapre “A current limiting device arranged along the power-supply bus may include a resistor”; see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”), wherein the control chip includes a semiconductor substrate (p-type doped substrate) including a first connecting region (the source/drain region of the p-channel transistor) connected to the first terminal (see [0025] of Kapre “a source/drain region of a p-channel transistor acts as an emitter, the n-well of the PMOS transistor acts as a base, and a p-type doped substrate acts as the collector”; see [0028] of Kapre “the pnpn diode structure is interposed between an anode and cathode, which are referenced as voltage sources Vcc and Vss”), and the first resistor element is arranged between the first connecting region and the first capacitor (the resistor RL is arranged along the power-supply bus 12 between the voltage source Vcc and the source/drain region of the p-channel transistor; see [0035] of Kapre “arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to include a first resistor element connected to the first terminal, wherein the control chip includes a semiconductor substrate including a first connecting region connected to the first terminal, the first resistor element is arranged between the first connecting region and the first capacitor, as taught by Kapre, because it can help prevent latch up of the parasitic bipolar transistors that are inherently contained in the integrated circuit chip of Maruyama and thereby improve the reliability of the control chip (see [0013] of Kapre “a CMOS circuit may be fabricated which is immune or free from latch up. As a result, the reliability of CMOS circuits may be improved.”).
Regarding claim 4, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first capacitor outside the control chip.
However, Kapre teaches (see Fig. 1a) the first resistor element (resistor RL) arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first capacitor (the resistor RL is arranged in the power supply path through which the voltage source Vcc supplies power to the circuit) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”; see [0035] of Kapre “arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit”), but does not disclose the first resistor element being arranged outside the control chip.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to arrange the first resistor element taught by Kapre between the first terminal and the first capacitor outside the control chip, because the first resistor element performs the same function of limiting the current supplied from the first capacitor to the first connecting region whether it is arranged inside or outside the control chip, and because arranging it outside the control chip can help provide the current limiting resistance without any alteration of the control chip, and since it has been held that the rearrangement of parts of an invention, where such a rearrangement does not modify the operation of the device, involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 5, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip.
However, Kapre teaches (see Fig. 1a) wherein the first resistor element (resistor RL) is arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first connecting region (the source/drain region of the p-channel transistor) inside the control chip (the resistor RL is formed along the power-supply bus 12 of the CMOS circuit 10) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip, as taught by Kapre, because it can help reduce the current drawn through the circuit of the control chip to a level below the holding current level of the parasitic pnpn diode structure formed in the semiconductor substrate (see [0033] of Kapre “the amount of current drawn through the respective circuits is reduced to a level below a holding current level of a pnpn diode structure in the circuits”).
Regarding claim 9, Maruyama discloses (see Fig. 1) wherein the control chip includes a second terminal (GND terminal) to which a reference potential is applied (see [0027] of Maruyama “A reference potential line GND is connected to a GND terminal of the control circuit 100.”).
Maruyama does not disclose wherein the semiconductor substrate includes a first parasitic transistor connected to the first connecting region, and the first terminal is connected to the second terminal via the first parasitic transistor.
However, Kapre teaches (see Fig. 1a) wherein the semiconductor substrate (p-type doped substrate) includes a first parasitic transistor (parasitic PNP bipolar transistor) connected to the first connecting region (the source/drain region of the p-channel transistor that acts as the emitter of the parasitic PNP bipolar transistor) (see [0025] of Kapre “a source/drain region of a p-channel transistor acts as an emitter, the n-well of the PMOS transistor acts as a base, and a p-type doped substrate acts as the collector”), and the first terminal is connected to the second terminal via the first parasitic transistor (the pnpn diode structure formed by the parasitic PNP bipolar transistor and the parasitic NPN bipolar transistor is interposed between the voltage source Vcc and the voltage source Vss) (see [0028] of Kapre “the pnpn diode structure is interposed between an anode and cathode, which are referenced as voltage sources Vcc and Vss”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein the semiconductor substrate includes a first parasitic transistor connected to the first connecting region, and the first terminal is connected to the second terminal via the first parasitic transistor, as taught by Kapre, because it can help implement the integrated circuit chip of Maruyama using CMOS technology, in which such parasitic bipolar transistors are inherently contained (see [0005] of Kapre “Integrated circuit semiconductor devices using CMOS technology inherently contain parasitic bipolar pnp and npn transistors”).
Claims 2, 3, 6-8, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama in view of Kapre, and further in view of Adragna (C. Adragna, “Offline Flyback Converters Design Methodology with the L6590 Family,” Application Note AN1262, STMicroelectronics, May 2001).
Regarding claim 2, Maruyama discloses (see Fig. 1) a switched-mode power supply (switching power source 200) comprising: a main transformer (transformer T1) (see [0017] of Maruyama “The switching power source 200 in the present example is provided with a primary side circuit 210, a secondary side circuit 220, and a transformer T1.”; see [0019] of Maruyama “The primary side circuit 210 has a control circuit 100, a primary side winding n1 of the transformer T1, a reset winding n3 of the transformer T1, a diode D1, and the switching element Q1.”); a switching device (switching element Q1) which performs switching control of a main current flowing through the main transformer (principal current flowing through the primary side winding n1) (see [0021] of Maruyama “The switching element Q1 is connected in series to the primary side winding n1, and is configured to perform switching control on whether a principal current is caused to flow through the primary side winding n1.”); a control chip (control circuit 100) which includes a first terminal (power source terminal VCC) and controls the switching device (see [0021] of Maruyama “The control circuit 100 is, for example, an integrated circuit chip.”; see [0021] of Maruyama “The control circuit 100 is configured to control the ON state and the OFF state of the switching element Q1.”; see [0024] of Maruyama “The primary side circuit 210 may have a power source circuit 230 configured to supply the source power to a power source terminal VCC of the control circuit 100.”); and a first capacitor (capacitor C8) which is connected to the first terminal of the control chip (see [0025] of Maruyama “The capacitors C8 and C9 are charged with the current having passed through the diode D5.”).
Maruyama does not disclose a first resistor element connected to the first terminal, wherein the control chip includes a semiconductor substrate including a first connecting region connected to the first terminal, and the first resistor element is arranged between the first connecting region and the first capacitor.
However, Kapre teaches (see Fig. 1a) a first resistor element (resistor RL) connected to the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) (see [0010] of Kapre “A current limiting device arranged along the power-supply bus may include a resistor”; see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”), wherein the control chip includes a semiconductor substrate (p-type doped substrate) including a first connecting region (the source/drain region of the p-channel transistor) connected to the first terminal (see [0025] of Kapre “a source/drain region of a p-channel transistor acts as an emitter, the n-well of the PMOS transistor acts as a base, and a p-type doped substrate acts as the collector”; see [0028] of Kapre “the pnpn diode structure is interposed between an anode and cathode, which are referenced as voltage sources Vcc and Vss”), and the first resistor element is arranged between the first connecting region and the first capacitor (the resistor RL is arranged along the power-supply bus 12 between the voltage source Vcc and the source/drain region of the p-channel transistor; see [0035] of Kapre “arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to include a first resistor element connected to the first terminal, wherein the control chip includes a semiconductor substrate including a first connecting region connected to the first terminal, and the first resistor element is arranged between the first connecting region and the first capacitor, as taught by Kapre, because it can help prevent latch up of the parasitic bipolar transistors that are inherently contained in the integrated circuit chip of Maruyama and thereby improve the reliability of the control chip (see [0013] of Kapre “a CMOS circuit may be fabricated which is immune or free from latch up. As a result, the reliability of CMOS circuits may be improved.”).
Maruyama does not disclose a first capacitor, a capacity value of which is greater than or equal to 5 µF and less than or equal to 100 µF.
However, Adragna teaches (see Fig. 7) a first capacitor (supply capacitor C) which is connected to the first terminal of the control chip (the capacitor C is connected to the Vcc pin of the L6590 monolithic switcher) and a capacity value of which is greater than or equal to 5 µF and less than or equal to 100 µF (22 µF) (see p. 20 of Adragna “A minimum value of 10 µF is recommended and any low cost electrolytic capacitor will do the job.”; see p. 37 of Adragna “The self supply circuit will include an 1N4148 diode and a 22 µF supply capacitor.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to include a first capacitor, a capacity value of which is greater than or equal to 5 µF and less than or equal to 100 µF, as taught by Adragna, because it can help keep the control chip running until the auxiliary winding develops its correct voltage at start-up (see p. 20 of Adragna “The supply capacitor has to be large enough to keep the device running during the time needed for the auxiliary winding to develop its correct voltage at start-up.”).
Regarding claim 3, Maruyama discloses (see Fig. 1) wherein the first terminal is a power supply terminal to which power supply electric power is supplied (the power source terminal VCC to which the source power is supplied from the power source circuit 230) (see [0024] of Maruyama “The primary side circuit 210 may have a power source circuit 230 configured to supply the source power to a power source terminal VCC of the control circuit 100.”).
Regarding claim 6, Maruyama does not disclose wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω.
However, Adragna teaches (see Fig. 7) a resistance value of a resistor (resistor Rs) that is connected in series in the supply path to the power supply terminal (Vcc) of a control chip (L6590 monolithic switcher) of 10 Ω (see p. 20 of Adragna “The resistor Rs in series to D filters the voltage spike appearing on the positive-going edge of the voltage generated by the self-supply winding”; see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω, as taught by Adragna, because a resistance value of this magnitude is conventional for a resistor connected in series in the power supply path of a control chip, and because it can help limit the current flowing from the first capacitor to the first connecting region to a level below the holding current level of the parasitic pnpn diode structure while keeping the voltage drop at the power supply terminal small (see [0012] of Kapre “sizing the current-limiting device such that the current through the second CMOS circuit does not exceed the holding current level”).
Regarding claim 7, Maruyama discloses (see Fig. 1) further comprising: an auxiliary winding (auxiliary winding n4) which supplies the power supply electric power to the first terminal (see [0024] of Maruyama “The power source circuit 230 in the present example has an auxiliary winding n4, a diode D5, a resistor R10, one or more capacitors (a capacitor C8 and capacitor C9 in the example of FIG. 1).”; see [0025] of Maruyama “Electrical power accumulated in the capacitors C8 and C9 is supplied as the source power of the control circuit 100.”); and a second resistor element (resistor R10) which is arranged between the auxiliary winding and the first capacitor (the resistor R10 is arranged in the path from the auxiliary winding n4 through the diode D5 to the capacitors C8 and C9 at the power source terminal VCC; see [0025] of Maruyama “The diode D5 is arranged between a high voltage side terminal of the auxiliary winding n4 and the power source terminal VCC of the control circuit 100”; see [0025] of Maruyama “The resistor R10 is arranged between the diode D5 and the power source terminal VCC.”).
Maruyama does not disclose a second resistor element, a resistance value of which is greater than or equal to 10 Ω and less than or equal to 100 Ω.
However, Adragna teaches (see Fig. 7) a resistance value of a resistor (resistor Rs) that is connected in series with the bias rectifier (diode D) between the self-supply winding (winding Naux) and the supply capacitor (capacitor C) at the power supply terminal (Vcc) of a control chip (L6590 monolithic switcher) of 10 Ω (see p. 20 of Adragna “The resistor Rs in series to D filters the voltage spike appearing on the positive-going edge of the voltage generated by the self-supply winding”; see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to include a second resistor element, a resistance value of which is greater than or equal to 10 Ω and less than or equal to 100 Ω, as taught by Adragna, because it can help filter the voltage spike that is generated in the auxiliary winding and reduce the variation of the voltage at the power supply terminal of the control chip with the load current (see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Regarding claim 8, Maruyama does not disclose further comprising: a second capacitor which is connected between the first resistor element and the first terminal and a capacity value of which is greater than or equal to 50 nF and less than or equal to 1000 nF.
However, Adragna teaches (see Fig. 19) a second capacitor (high-frequency filter capacitor with a plastic film or ceramic dielectric) which is connected between the first resistor element and the first terminal (the filter capacitor is placed between the Vcc pin of the control chip and the signal ground route illustrated in Fig. 19, as close to the integrated circuit as possible, and therefore on the terminal side of the resistance in the supply path) (see p. 32 of Adragna “Some crucial points of the circuit need or may need filtering, such as the VCC pin or the BOK pin.”; see p. 32 of Adragna “as close to the IC as possible”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to further comprise a second capacitor which is connected between the first resistor element and the first terminal and a capacity value of which is greater than or equal to 50 nF and less than or equal to 1000 nF, as taught by Adragna, because it can help filter the high frequency noise appearing at the power supply terminal of the control chip, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Examiner’s Note: consistent with the objection to claim 8 above, the recited second capacitor is interpreted as being connected to the wiring between the first resistor element and the first terminal, as described in paragraph [0060] of the instant specification.
Regarding claim 11, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first capacitor outside the control chip.
However, Kapre teaches (see Fig. 1a) the first resistor element (resistor RL) arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first capacitor (the resistor RL is arranged in the power supply path through which the voltage source Vcc supplies power to the circuit) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”; see [0035] of Kapre “arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit”), but does not disclose the first resistor element being arranged outside the control chip.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to arrange the first resistor element taught by Kapre between the first terminal and the first capacitor outside the control chip, because the first resistor element performs the same function of limiting the current supplied from the first capacitor to the first connecting region whether it is arranged inside or outside the control chip, and because arranging it outside the control chip can help provide the current limiting resistance without any alteration of the control chip, and since it has been held that the rearrangement of parts of an invention, where such a rearrangement does not modify the operation of the device, involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 12, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip.
However, Kapre teaches (see Fig. 1a) wherein the first resistor element (resistor RL) is arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first connecting region (the source/drain region of the p-channel transistor) inside the control chip (the resistor RL is formed along the power-supply bus 12 of the CMOS circuit 10) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip, as taught by Kapre, because it can help reduce the current drawn through the circuit of the control chip to a level below the holding current level of the parasitic pnpn diode structure formed in the semiconductor substrate (see [0033] of Kapre “the amount of current drawn through the respective circuits is reduced to a level below a holding current level of a pnpn diode structure in the circuits”).
Regarding claim 13, Maruyama does not disclose wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω.
However, Adragna teaches (see Fig. 7) a resistance value of a resistor (resistor Rs) that is connected in series in the supply path to the power supply terminal (Vcc) of a control chip (L6590 monolithic switcher) of 10 Ω (see p. 20 of Adragna “The resistor Rs in series to D filters the voltage spike appearing on the positive-going edge of the voltage generated by the self-supply winding”; see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω, as taught by Adragna, because a resistance value of this magnitude is conventional for a resistor connected in series in the power supply path of a control chip, and because it can help limit the current flowing from the first capacitor to the first connecting region to a level below the holding current level of the parasitic pnpn diode structure while keeping the voltage drop at the power supply terminal small (see [0012] of Kapre “sizing the current-limiting device such that the current through the second CMOS circuit does not exceed the holding current level”).
Regarding claim 14, Maruyama discloses (see Fig. 1) further comprising: an auxiliary winding (auxiliary winding n4) which supplies the power supply electric power to the first terminal (see [0024] of Maruyama “The power source circuit 230 in the present example has an auxiliary winding n4, a diode D5, a resistor R10, one or more capacitors (a capacitor C8 and capacitor C9 in the example of FIG. 1).”; see [0025] of Maruyama “Electrical power accumulated in the capacitors C8 and C9 is supplied as the source power of the control circuit 100.”); and a second resistor element (resistor R10) which is arranged between the auxiliary winding and the first capacitor (the resistor R10 is arranged in the path from the auxiliary winding n4 through the diode D5 to the capacitors C8 and C9 at the power source terminal VCC; see [0025] of Maruyama “The diode D5 is arranged between a high voltage side terminal of the auxiliary winding n4 and the power source terminal VCC of the control circuit 100”; see [0025] of Maruyama “The resistor R10 is arranged between the diode D5 and the power source terminal VCC.”).
Maruyama does not disclose a second resistor element, a resistance value of which is greater than or equal to 10 Ω and less than or equal to 100 Ω.
However, Adragna teaches (see Fig. 7) a resistance value of a resistor (resistor Rs) that is connected in series with the bias rectifier (diode D) between the self-supply winding (winding Naux) and the supply capacitor (capacitor C) at the power supply terminal (Vcc) of a control chip (L6590 monolithic switcher) of 10 Ω (see p. 20 of Adragna “The resistor Rs in series to D filters the voltage spike appearing on the positive-going edge of the voltage generated by the self-supply winding”; see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to include a second resistor element, a resistance value of which is greater than or equal to 10 Ω and less than or equal to 100 Ω, as taught by Adragna, because it can help filter the voltage spike that is generated in the auxiliary winding and reduce the variation of the voltage at the power supply terminal of the control chip with the load current (see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Regarding claim 15, Maruyama does not disclose further comprising: a second capacitor which is connected between the first resistor element and the first terminal and a capacity value of which is greater than or equal to 50 nF and less than or equal to 1000 nF.
However, Adragna teaches (see Fig. 19) a second capacitor (high-frequency filter capacitor with a plastic film or ceramic dielectric) which is connected between the first resistor element and the first terminal (the filter capacitor is placed between the Vcc pin of the control chip and the signal ground route illustrated in Fig. 19, as close to the integrated circuit as possible, and therefore on the terminal side of the resistance in the supply path) (see p. 32 of Adragna “Some crucial points of the circuit need or may need filtering, such as the VCC pin or the BOK pin.”; see p. 32 of Adragna “as close to the IC as possible”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to further comprise a second capacitor which is connected between the first resistor element and the first terminal and a capacity value of which is greater than or equal to 50 nF and less than or equal to 1000 nF, as taught by Adragna, because it can help filter the high frequency noise appearing at the power supply terminal of the control chip, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Examiner’s Note: consistent with the objection to claim 15 above, the recited second capacitor is interpreted as being connected to the wiring between the first resistor element and the first terminal, as described in paragraph [0060] of the instant specification.
Regarding claim 16, Maruyama discloses (see Fig. 1) wherein the control chip includes a second terminal (GND terminal) to which a reference potential is applied (see [0027] of Maruyama “A reference potential line GND is connected to a GND terminal of the control circuit 100.”).
Maruyama does not disclose wherein the semiconductor substrate includes a first parasitic transistor connected to the first connecting region, and the first terminal is connected to the second terminal via the first parasitic transistor.
However, Kapre teaches (see Fig. 1a) wherein the semiconductor substrate (p-type doped substrate) includes a first parasitic transistor (parasitic PNP bipolar transistor) connected to the first connecting region (the source/drain region of the p-channel transistor that acts as the emitter of the parasitic PNP bipolar transistor) (see [0025] of Kapre “a source/drain region of a p-channel transistor acts as an emitter, the n-well of the PMOS transistor acts as a base, and a p-type doped substrate acts as the collector”), and the first terminal is connected to the second terminal via the first parasitic transistor (the pnpn diode structure formed by the parasitic PNP bipolar transistor and the parasitic NPN bipolar transistor is interposed between the voltage source Vcc and the voltage source Vss) (see [0028] of Kapre “the pnpn diode structure is interposed between an anode and cathode, which are referenced as voltage sources Vcc and Vss”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein the semiconductor substrate includes a first parasitic transistor connected to the first connecting region, and the first terminal is connected to the second terminal via the first parasitic transistor, as taught by Kapre, because it can help implement the integrated circuit chip of Maruyama using CMOS technology, in which such parasitic bipolar transistors are inherently contained (see [0005] of Kapre “Integrated circuit semiconductor devices using CMOS technology inherently contain parasitic bipolar pnp and npn transistors”).
Regarding claim 18, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first capacitor outside the control chip.
However, Kapre teaches (see Fig. 1a) the first resistor element (resistor RL) arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first capacitor (the resistor RL is arranged in the power supply path through which the voltage source Vcc supplies power to the circuit) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”; see [0035] of Kapre “arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit”), but does not disclose the first resistor element being arranged outside the control chip.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama to arrange the first resistor element taught by Kapre between the first terminal and the first capacitor outside the control chip, because the first resistor element performs the same function of limiting the current supplied from the first capacitor to the first connecting region whether it is arranged inside or outside the control chip, and because arranging it outside the control chip can help provide the current limiting resistance without any alteration of the control chip, and since it has been held that the rearrangement of parts of an invention, where such a rearrangement does not modify the operation of the device, involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 19, Maruyama does not disclose wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip.
However, Kapre teaches (see Fig. 1a) wherein the first resistor element (resistor RL) is arranged between the first terminal (the power-supply bus 12 that is coupled to the voltage source Vcc) and the first connecting region (the source/drain region of the p-channel transistor) inside the control chip (the resistor RL is formed along the power-supply bus 12 of the CMOS circuit 10) (see [0024] of Kapre “FIG. 1a illustrates resistor RL formed along power-supply bus 12 of CMOS circuit 10”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein the first resistor element is arranged between the first terminal and the first connecting region inside the control chip, as taught by Kapre, because it can help reduce the current drawn through the circuit of the control chip to a level below the holding current level of the parasitic pnpn diode structure formed in the semiconductor substrate (see [0033] of Kapre “the amount of current drawn through the respective circuits is reduced to a level below a holding current level of a pnpn diode structure in the circuits”).
Regarding claim 20, Maruyama does not disclose wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω.
However, Adragna teaches (see Fig. 7) a resistance value of a resistor (resistor Rs) that is connected in series in the supply path to the power supply terminal (Vcc) of a control chip (L6590 monolithic switcher) of 10 Ω (see p. 20 of Adragna “The resistor Rs in series to D filters the voltage spike appearing on the positive-going edge of the voltage generated by the self-supply winding”; see p. 37 of Adragna “A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switched-mode power supply of Maruyama wherein a resistance value of the first resistor element is greater than or equal to 10 Ω and less than or equal to 100 Ω, as taught by Adragna, because a resistance value of this magnitude is conventional for a resistor connected in series in the power supply path of a control chip, and because it can help limit the current flowing from the first capacitor to the first connecting region to a level below the holding current level of the parasitic pnpn diode structure while keeping the voltage drop at the power supply terminal small (see [0012] of Kapre “sizing the current-limiting device such that the current through the second CMOS circuit does not exceed the holding current level”).
Allowable Subject Matter
Claims 10 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the semiconductor substrate includes a protection element which is provided between the first terminal and the second terminal and causes a current to flow from the first terminal to the second terminal when a voltage at the first terminal exceeds an upper limit voltage, a second connecting region connected to the second terminal, and a second parasitic transistor which causes a current to flow through the protection element according to a potential of the second connecting region.”.
The closest prior art, Maruyama, discloses a protective diode that clamps the voltage at the power source terminal VCC so that the voltage does not become equal to or more than a predetermined voltage (see [0041] of Maruyama “The protective diode 14 is configured to clamp a VCC voltage such that a voltage at the VCC terminal does not become equal to or more than a predetermined voltage.”), and Kapre discloses parasitic bipolar transistors that are inherently contained in a CMOS structure (see [0005] of Kapre “Integrated circuit semiconductor devices using CMOS technology inherently contain parasitic bipolar pnp and npn transistors”), but neither discloses a second connecting region connected to the second terminal, nor a second parasitic transistor which causes a current to flow through the protection element according to a potential of the second connecting region.
Regarding claim 17, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the semiconductor substrate includes a protection element which is provided between the first terminal and the second terminal and causes a current to flow from the first terminal to the second terminal when a voltage at the first terminal exceeds an upper limit voltage, a second connecting region connected to the second terminal, and a second parasitic transistor which causes a current to flow through the protection element according to a potential of the second connecting region.”. The reasons are the same as those given for claim 10 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2022/0311346 A1 discloses a power supply control device in which a switch and a resistor are coupled in series between a power supply terminal of a control circuit and a ground.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838
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