Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment, filed 8/14/26.
Claims 1-2, 4-10, 12-15, 17, and 19-24 are pending.
Response to Arguments
Applicant has amended the claims to include new limitations not previously considered. The amended claims require new search and consideration. In view of the amendment, the previous 35 USC 102 rejection to claims 1-20 is withdrawn. The amended claims are addressed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-10, 12-15, 17, and 19-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US20210365183A1) in view of Pitchumani (US20240361952A1)
As to claim 1, 8, 15:
Byun teaches a method (method of operation; [0006], [0017], [0018]) operating a data structure by a processor a host and memory system ([0058], [0075]) processor in which the host logically organizes the memory into logical blocks and segments and performs segment recycling on the data structure, obtaining blocks of the data structure from a storage device ([0008,], [0017], [0019], file system FS manages memory device and the structure in which files are stored [0109], the log file system LFS divides the storage area into a plurality of areas [0110]), and performing modification/cleaning operation involving valid portions of stored blocks ([0008], [0017], [0109]-[0112], [0116]-[0122], [0146]-[0149]).
Byun does not expressly teach transferring to a cache of the at least one processor, [valid/access data information] from a storage device, using [valid/access data information] and a load command of a memory access technique. Valid/access information is broadly interpreted as data transferred in Byun ([0005]-[0008], [0036-0038]). It is well-known in the art to issue load/store instructions for memory accessing.
Pitchumani teaches accessing data stored in storage media cache ([0028], [0030], [0038]-[0043])using memory load/store instructions and teaches issuing a memory load command transferring the requested data using memory access protocol ([0043]. Pitchumani discloses memory load/store requests can be translated into storage read/write requests, [0047]-[0048], and expressly teaches that a memory-access request to load a cache line causes a page containing the requested cache line to be read from storage media and placed in a cache, after which the requested cache line is loaded from the cache ([0048]). For a memory load operation, Pitchumani teaches issuing memory load/store instructions using CXL.mem, [0077], upon a cache miss, reading the page/block/sector containing the requested data from storage media, optionally placing it in a cache, and returning the requested byte/word/cache line, [0080], and servicing a memory load command for data in storage media by reading the containing page/block/sector into cache, extracting the requested data, and returning it in response to the memory load command, [0140]-[0143].
Pitchumani identifies reduced latency, bandwidth improvement, reduced power consumption, and reduced data transfer as benefits of its CXL memory access arrangement.
It would have been obvious to one of ordinary skills in the art, at the time of the invention, to implement the host/storage access of Byun using the memory access mechanism of Pichumani in order to provide more direct host access to storage data and reduce data transfer overhead and latency.
Byun further teaches merging a first portion and second portion of the one or more blocks of data through segment recycling ([0008], [0017]-[0020]). Byun teaches that individual memory blocks contain both valid and invalid data, [0042], and that garbage collection selects a target block, copies valid data from the selected block and moves the valid data to another memory block, updates the map information, and erases the selected block, [0043], and copying valid data remaining in a dirty block into a free block, [0051]. The consolidation of storage portions during garbage collection and segment recycling reads on the merging of different data portions.
As to claim 2, 9, 17:
Byun teaches the modification operation comprises a cleaning operation (garbage collection which involves selecting a target memory block, copying its valid data to another memory block, updating mapping information, and erasing the selected memory block [0017]-[0020], [0042]-[0044], [0112]-[0113].)
As to claim 4, 10:
Byun teaches performing the modification is based at least in part, on location information for the one or more blocks of data or size information (host obtains identification information for the memory blocks from the memory system and uses that information together with valid information to determine the valid logical blocks corresponding to each memory block. [0009], [0018]; identify memory block using logical block addresses, physical page addresses, newly allocated logical block addresses, and identification information for the target memory block [0010]-[0015]).
As to claim 5:
Byun teaches receiving by the processor, from the storage device, first information about the blocks (host obtains valid information corresponding to the logical blocks and identification information for the memory blocks from the memory system [0009], [0018]); and
generating from that information second information about blocks resulting from the merging (host uses the received information to calculate the number of valid logical blocks corresponding to each memory block, [0009], [0018], allocates new logical block addresses to valid logical blocks during segment recycling, [0013], [0018], and matches target-memory-block identification information with the valid logical block having the new address, [0018]).
As to claim 6:
Byun teaches generating a result of the merging; and transferring at least a portion of the result to the storage device (during segment recycling the host allocates a new logical block address to valid data and transmits to the memory system a write request for the data corresponding to the valid logical block, [0013]; the memory system then performs the write operation on a target memory block, [0014], [0018]; copying valid data into a free block, [0043], [0051]).
As to claim 7:
Pitchumani further teaches a processor-to-storage-device fetch request (commands for prefetching data from storage medium 304 to cache 310, [0070]-[0072]; commands may move data between host memory and device memory and may prefetch data from storage medium 304 to cache 310, [0071]), and, based upon that request, loading data at the storage device from storage medium to memory (reading the page/block/sector containing requested data from storage media, storing it in a cache, and extracting the requested data from that cache; [0141]).
As to claim 12:
Byun teaches sending, from the storage device to the processor, information about the blocks of data (host obtains valid information corresponding to the logical blocks and identification information for the memory blocks from the memory system, and calculates the number of valid logical blocks corresponding to each memory block based on that information; [0009], host checks the number of valid logical blocks and memory-block identification information MBLK_ID [0158]); and generating, by the processor, based on that information, the valid-data information (calculates the number of valid logical blocks corresponding to respective memory blocks based on those items [0159]).
As to claim 13:
Byun teaches valid-data information comprising destination information for merged data (host obtains valid information and memory-block identification information from the memory system [0009], [0018]. That information identifies the existing/source blocks.);
Sending, from the storage device to the processor, source information for stored data (host then allocates a new logical block address to a valid logical block included in the victim segment and sends a write request for the data corresponding to the valid logical block [0013]. The memory system writes the data into a target memory block and sends identification information for that target block to the host [0014]-[0015]); and processor generating the destination information based on the source information (host identifies current valid data and allocates a new LBA for migrated data; [0149]-[0151]).
As to claim 14:
Pitchumani teaches sending, from the processor to the storage device, a fetch request (user sending a prefetch request to cache/prefetch logic, the logic to store a copy of data from storage in cache [0086]; accepting commands for data movement/cache management [0070];
data-movement commands including prefetching data from storage medium 304 to cache 310 [0071]; cache-management operations including prefetching [0072]);
loading, at the storage device, based on the fetch request, from a storage medium to a memory, at least a portion of the one or more blocks of data (storage data being read as a page/block/sector and temporarily stored in a cache [0080]; servicing a memory-load command by reading a page/block/sector from storage media and placing it into cache [0141]; and a memory-load request resulting in a storage read, with the resulting page stored in cache [0143]).
Byun teaches performing the modification operation on the portion(s) of blocks of data in the memory merging a first portion and second portion of the one or more blocks of data through segment recycling ([0008], [0017]-[0020]). Byun teaches that individual memory blocks contain both valid and invalid data, [0042], and that garbage collection selects a target block, copies valid data from the selected block and moves the valid data to another memory block, updates the map information, and erases the selected block, [0043], and copying valid data remaining in a dirty block into a free block, [0051]. The consolidation of storage portions during garbage collection and segment recycling reads on the merging of different data portions.
As to claim 19:
Byun teaches the modification operation generates a result (merging a first portion and second portion of the one or more blocks of data through segment recycling ([0008], [0017]-[0020]), and at least part of that result is stored in memory at the host (host memory 106 may temporarily store data read from the memory system 110 and data to be written to the memory system 110; [0117]; During segment recycling, data corresponding to the valid logical block is copied into the free segment [0112]-[0113], and the host requests the memory system to read the current data, receives it, allocates a new logical address, and requests that the data be written to the new location [0150]-[0151]).
As to claim 20:
Byun teaches the modification operation generates a result, and further sending the result to the storage device (during segment recycling, the host block address, [0150]-[0151], transmits to the memory system a write request for the corresponding data [0013], after which the memory system writes the data into the target memory block [0014]). Pitchumani additionally teaches write-through and write-back operations that transfer modified/cached data to storage media (0041], [0078], [0080]).
As to claim 21:
Byun teaches valid data information is a copy list (lists in other contexts and plainly discloses copying valid pages/data during GC, e.g., [0098], [0100], [0112]-[0113]).
As to claim 22:
Byun teaches information about the blocks comprises first metadata (metadata-like information: logical/physical address mappings, block identification information, valid-block information and mapping-table updates. [0009]-[0018], [0096]-[0100], [0158]-[0159]), generating, by a metadata merge operation, second metadata about merged data, and sending from the processor to the storage second metadata merging a first portion and second portion of the one or more blocks of data through segment recycling ([0008], [0017]-[0020]). Byun teaches that individual memory blocks contain both valid and invalid data, [0042], and that garbage collection selects a target block, copies valid data from the selected block and moves the valid data to another memory block, updates the map information, and erases the selected block, [0043], and copying valid data remaining in a dirty block into a free block, [0051].
As to claim 23:
Pitchumani teaches the access pattern comprise frequency of access or a recency of access( (LRU) eviction policy, under which recently used data is retained in cache because recently used data may likely be accessed again [0078]).
As to claim 24:
Pitchumani teaches the second portion is received at a cache of the processor at the host using a load command of a memory access technique (memory load/store instructions using CXL.mem [0077]; storage media may be accessed as memory through a second data-transfer mechanism, such as CXL.mem, [0140]; an application accesses storage media as memory using memory load/store instructions with CXL.mem, [0141]; a storage device services a memory load command by reading the containing page/block/sector from storage media, storing it in cache, extracting the requested data, and returning the requested data, [0141]; an application may send a memory load command using CXL to storage, with cache servicing the request,[0143]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
