DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10, Line 1, “The c according to claim 1” is expected to read “the circuit according to claim 1”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 8, 11, & 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "a fixed ratio N" in line 2. The claim as written is unclear. A fixed ratio N has been previously introduced in claim 1, of which claim 2 depends upon. Further clarification is necessary. For examination purposes, examiner has interpreted “a fixed ratio N” to read “the fixed ratio N”.
By virtue of its dependency on claim 2. Claim 3 is also rejected.
Claim 8 recites the limitation “the control circuit” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the control circuit” to read “the voltage control circuit”.
Claim 11 recites the limitation “the first circuit” in lines 40 and “the second circuit” in line 41. There is insufficient antecedent basis for the limitations in the claim. For examination purposes, examiner has interpreted “the first circuit” to read “the first data transmission circuit” and “the second circuit” to read “the second data transmission circuit”.
Claim 13 recites the limitation "a fixed ratio N" in line 3. The claim as written is unclear. A fixed ratio N has been previously introduced in claim 12, of which claim 13 depends upon. Further clarification is necessary. For examination purposes, examiner has interpreted “a fixed ratio N” to read “the fixed ratio N”.
By virtue of its dependency on claim 13. Claim 14 is also rejected.
Allowable Subject Matter
Claims 1, 3-7, 9-10, 12, & 14 are allowed.
Regarding claim 1, Fujita et al. (US 2018/0316366 A1), hereinafter Fujita, discloses, in figure 4, a data transmission circuit, comprising:
an output branch (13) comprising a first resistor (81), a first transistor (Para [0056], “switch 85…can be configured using a single MOS transistor”), and a second transistor (83) series-connected between a first voltage rail and a first output node (series-connected between Vdd and output node 16), the second transistor being configured to receive on its gate a data signal (Para [0056], “signal Tx_data to be transmitted…is inputted to a gate of…PMOS transistor 83”); and
a branch of duplication of the output branch with equal dimensions (duplicated branch 14), or with dimensions having a fixed ratio N, with respect to the output branch, the duplication branch comprising a second resistor (82), a third transistor (Para [0056], “switch…86 can be configured using a single MOS transistor”), and a fourth transistor (84) series-connected between the first voltage rail and a second node (series-connected between Vdd and a second node Vss), the fourth transistor being configured to receive on its gate the data signal (Para [0056], “signal Tx_data to be transmitted…is inputted to a gate of…NMOS transistor 84”).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
a current source coupling the second node and a second voltage rail, the current source generating a current; and a voltage control circuit comprising an input coupled to the second node and configured to control a gate voltage of the first and third transistors based on a reference voltage.
Claim 12 is allowed because Fujita discloses the identical limitations as recited in claim 1 and shown above, however, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
generating a current by a current source coupling the second node and a second voltage rail; and controlling a gate voltage of the first and third transistors based on a reference voltage by a voltage control circuit comprising an input coupled to the second node.
Claim 11 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 11 would be allowable because Fujita discloses the identical limitations as recited in claim 1 and shown above, however, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
The first data transmission circuit comprising a current source coupling the second node and a second voltage rail; and a voltage control circuit comprising an input coupled to the second node and configured to control a gate voltage of the first and third transistors based on a reference voltage; and
The second data transmission circuit comprising a voltage control circuit comprising an input coupled to the second node and configured to control a gate voltage of the first and third transistors based on a reference voltage, wherein the current source of the first data transmission circuit couples the second node of the second data transmission circuit and the first voltage rail.
Claims 2-3, 8, & 13-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsu et al. (US 7,233,177 B2) [Figure 2. Discloses a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.]
Gabara (US 5,977,796) [Figure 4C. Discloses A low voltage differential swing interconnect I/O buffer within an output buffer part comprising a voltage controlled current source, voltage controlled current sink, and a current switch and an input buffer part comprising a voltage controlled resistance. The output current and input resistance of the I/O buffer is determined by biasing voltages which are generated by on-chip reference circuits and applied to the voltage controlled components of the I/O buffer. Using two input reference voltages and a single reference resistor, the reference circuits dynamically adjust the biasing voltages so that the I/O buffer maintains the required output current and input resistance for all manufacturing process, supply voltage, and chip temperature variations.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
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