Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 2-3 and 5-21 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-2 and 4-20 of prior U.S. Patent No. 12,307,116. This is a statutory double patenting rejection. Regarding the bolded difference below of “transferring the second data to the nonvolatile memory”, paragraph 5 of the current specification recites that “the write process includes a process of transferring user data from the controller 4 to the NAND flash memory 5…”. Therefore, the additional of the transferring language is merely a restatement of the writing operation of the Patent. The additional difference of “that is obtained by” does not create any significant difference between the two claims that would qualify the current claims as a new invention.
19/185,755
Patent 12,307,116
2. A memory system comprising:
a nonvolatile memory; and
a controller configured to:
manage a first time length that is obtained by subtracting a second time length from a third time length, the third time length being designated by a host as a time limit of transmission of a first response since reception of a first write request, the second time length corresponding to a time length when data becomes readable from the nonvolatile memory after a write process of the data to the nonvolatile memory is started;
in response to fetching the first write request associated with first data from the host, the first data having a size less than a first data unit that is a write unit to the nonvolatile memory, start to measure a time period;
in response to the measured time period reaching the first time length, start a write process of second data to the nonvolatile memory by transferring the second data to the nonvolatile memory, the second data including at least the first data, the second data having a size of the first data unit; and
in response to completion of the write process of the second data, transmit the first response for the first write request to the host.
1. A memory system comprising:
a nonvolatile memory; and
a controller configured to:
manage a first time length by subtracting a second time length from a third time length, the third time length being designated by a host as a time limit of transmission of a first response since reception of a first write request, the second time length corresponding to a time length when data becomes readable from the nonvolatile memory after a write process of the data to the nonvolatile memory is started;
in response to fetching the first write request associated with first data from the host, the first data having a size less than a first data unit that is a write unit to the nonvolatile memory, start to measure a time period;
in response to the measured time period reaching the first time length, start a write process of second data to the nonvolatile memory, the second data including at least the first data, the second data having a size of the first data unit; and
in response to completion of the write process of the second data, transmit the first response for the first write request to the host.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,307,116. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patent would anticipate those of the current application.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,307,116 in view of Meena et al. (Overview of emerging nonvolatile memory technologies).
19/185,755
Patent 12,307,116
4. The memory system according to claim 2, wherein the nonvolatile memory includes a memory cell, and the write process of the second data includes the transferring of the second data to the nonvolatile memory and programming of the second data to the memory cell.
3. The memory system according to claim 2, wherein the controller is configured to, in starting the write process of the second data, fetch the first data from the host.
Regarding claim 4, claim 3 of Patent 12,307,116 discloses the memory system according to claim 2, as well as the transfer of data from the host to the nonvolatile memory.
Patent 12,307,116 fails to teach that the nonvolatile memory includes a cell and data is written to the cell.
Meena discloses an overview of nonvolatile memory technologies. Nonvolatile memory may be implemented using a cell architecture, and data is written to the cells [see Fig. 1 & Classification of solid-state memory technologies].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the cell based nonvolatile memory of Meena in the system of Patent 12,307,116.
The motivation for doing so would have been to reach higher capacities with in less space and power consumption [see Meena, general overview].
Therefore, it would have been obvious to combine Meena with Patent 12,307,116 for the benefits listed above, to obtain the invention as specified in claim 4.
Allowable Subject Matter
Claims 2-21 would be allowable over the prior art of record, provided all Double Patenting issues are properly overcome. The prior art of record including the disclosure of Mandal (US 2007/0079044) generally teaches a holdoff time when writing to memory, the time is defined such that expiration of timer occurs when waiting longer would introduce latency that is not expected to be offset by the efficiency gain from merging requests. Hsiao (US 2020/0110555) generally teaches a nonvolatile storage device in which includes a write buffer. A controller waits until a for a time length threshold and an amount of data to accumulate in the buffer before writing the data to nonvolatile memory. However, none of the prior art of record anticipates nor renders obvious the claim limitations directed towards the host designating the value of the third time and the second time corresponding to time when data becomes readable from the nonvolatile memory after a write process of the data to the nonvolatile memory is started.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Renesas (Tsi350 PCI-to-PCI Bridge User Manual) – Generally teaches a PCI interconnected storage system in which a delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states.
Cheung (US 8,942,248) – Generally teaches determining a time difference between the start of a cycle for receiving data in a channel of nonvolatile memory and the start of transmitting of the data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN BERTRAM/Primary Examiner, Art Unit 2137