Prosecution Insights
Last updated: August 17, 2026
Application No. 19/185,954

SOLAR CELL, PREPARATION METHOD THEREOF, AND PHOTOVOLTAIC MODULE

Final Rejection §103
Filed
Apr 22, 2025
Priority
Nov 26, 2024 — CN 202411708348.6
Examiner
TRINH, THANH TRUC
Art Unit
1726
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Zhejiang Jinko Solar Co., Ltd.
OA Round
2 (Final)
22%
Grant Probability
At Risk
3-4
OA Rounds
2y 11m
Est. Remaining
33%
With Interview

Examiner Intelligence

Grants only 22% of cases
22%
Career Allowance Rate
178 granted / 809 resolved
-43.0% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
4y 3m
Avg Prosecution
47 currently pending
Career history
875
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
49.7%
+9.7% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
26.5%
-13.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 809 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claims The amendment to claims filed on 4/27/2026 is acknowledged. Claims 1, 10, 13, and 15 are amended. Claim 14 is canceled. Currently, claims 1-13 and 15-20 are pending in the application. Previous 112 rejections are withdrawn in view of the above amendment. Previous prior art rejection is withdrawn in view of the above amendment. Claims 1-13 and 15-20 are rejected on a new ground of rejection. See the rejection below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. as applied to claim 1 above, in view of Yamamoto et al. (US 2015/0221801), and further in view of Seo et al. (US 2013/0146136). Regarding claim 1, Chen et al. discloses a solar cell (figs. 1-2) comprising a substrate (11, figs. 1 and 2, [0113]) having a front surface and a back surface disposed opposite to each other, wherein the back surface of the substrate comprising: a first doped region (see first region 12) comprising a doped polysilicon passivation contact structure (see first doped semiconductor 15, first passivation layer 29, and first electrode 27; figs. 1-2; [0104] and [0184]) disposed therein; a second doped region (see second region 13) that is spaced apart from the first doped region (12), and comprising a doped amorphous silicon structure (see second doped semiconductor layer 16, second passivation layer 30 and second electrode 28; figs. 1-2; [0104] and [0186]) disposed therein; and an insulating region (or spacing regiong14) disposed between the first doped region (12) and the second doped region (13), and comprising a passivation layer (see first dielectric layer 17 and second dielectric layer 18, [0104]) disposed therein (see figs. 1 and 2); wherein: the doped polysilicon passivation contact structure (15/29/27) comprises a tunneling oxide layer (or first passivation layer 29, [0183-0184] and [0282]), a doped polysilicon layer (or the first doped semiconductor 15, [0184]) that are stacked on the back surface of the substrate (11) sequentially (see figs. 1-2), and a first electrode/conducting layer (27) on a side of the doped polysilicon layer (15) away from the substrate (11, see figs. 1-2); the doped amorphous silicon structure (16/30/28) comprises a doped amorphous silicon layer (or second doped semiconductor 16, [0186]), an intrinsic amorphous silicon layer (see second passivation layer 30, [0104] and [0186]) disposed on a side of the doped amorphous silicon layer (16) adjacent to the substrate (11, see figs. 1-2), and a second electrode/conducting layer (28) disposed on a side of the doped amorphous silicon layer (16) away from the substrate (11, see figs. 1-2); the doped polysilicon layer (or first doped semiconductor of doped polycrystalline silicon) and the doped amorphous silicon layer (or second doped semiconductor of doped amorphous) have different doping types (or opposite conductivity types, [0005], [0116] and [0119]); and the passivation layer (17/18) is not overlapped with the doped polysilicon passivation contact structure (15/29/27) or the doped amorphous silicon structure (16/30/28) along a thickness direction of the substrate (11, see figs. 1-2). Chen et al. does not teach the intrinsic amorphous silicon layer to be a hydrogenated amorphous silicon layer. Yamamoto et al. teaches using intrinsic amorphous silicon layer (5) disposed on a side of the doped amorphous silicon layer (6 or 8) adjacent to the substrate (1, see fig. 1), wherein the amorphous silicon encompasses the hydrogenated amorphous silicon with the dangling bond of the silicon atoms being terminated/passivated with hydrogen for amorphous silicon (see [0078]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have used intrinsic hydrogenated amorphous silicon for the intrinsic amorphous silicon as taught by Yamamoto et al., because Yamamoto et al. teaches hydrogenated amorphous silicon having silicon atoms being terminated/passivated with hydrogen (or better amorphous silicon). Such modification would involve nothing more than use of known material for its intended use in a known environment to accomplish entirely expected result. International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007). The Courts have held that the selection of a known material, which is based upon its suitability for the intended use, is within the ambit of one ordinary skill in the art. See In re Leshin, 125 USPQ 416 (CCPA 1960) (See MPEP 2144.07). Chen et al. does not teach including a first transparent conducting layer and a second transparent conducting layer as claimed. Seo et al. discloses including a first transparent conducting layer (see ’33, figs. 1, 3K and 6, [0049]) disposed on a side of the first semiconductor layer (‘32) away from the substrate (‘10, see figs. 1, 3K and 6), and a second transparent conducting layer (see ’43, figs. 1, 3K, and 6, [0053]) disposed on the side of the second semiconductor layer (’42) away from the substrate (’10, see figs. 1, 3K and 6) to reduce contact resistance with the first electrode (’51) and the second electrode (’52, see [0049] and [0053]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the solar cell of Chen et al. by incorporating a first transparent conducting layer on a side of the doped polysilicon layer (or the first semiconductor layer) away from the substrate and a second transparent conducting layer on a side of the doped amorphous silicon layer (or the second semiconductor layer) away from the substrate to reduce contact resistance with the electrode as taught by Seo et al. Regarding claim 2, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. discloses a surface (or bottom surface shown in figs. 1-2) of the tunneling layer (29) adjacent to the substrate is lower than each of a surface (or bottom surface shown in figs. 1-2) of the doped amorphous silicon structure (16/30/28) adjacent to the substrate and a surface (or the bottom surface shown in figs. 1-2) of the passivation layer (17/18) adjacent to the substrate (11) along a preset direction, and the preset direction is a direction from the front surface (or the bottom surface shown in figs. 1-2) of the substrate (11) to the back surface (or the top surface shown in figs. 1-2) of the substrate (11, see figs. 1-2). Regarding claim 3, modified Chen et al. discloses a solar cell according to claim 2, wherein Chen et al. teaches the surface of the doped amorphous silicon layer (16) adjacent to the substrate (11) is flush with (or abutted) the surface of the passivation layer (17/18) adjacent to the substrate (see figs. 1-2 and [0122]). Regarding claim 4, modified Chen et al. discloses a solar cell as in claim 2 above, wherein Chen et al. teaches forming the groove such that the portion of the bottom surface of the groove structure corresponding to the spacing region (14) is lower than the portion of the bottom surface of the groove structure that corresponds to the second region (13, see [0122]). As such, Chen et al. teaches the surface of the passivation layer (17/18 in the spacing region 14) adjacent to the substrate is higher than the surface of the doped amorphous silicon structure (16/30/28 in the second region 13) adjacent to the substrate along the preset direction. Regarding claim 5, modified Chen et al. discloses a solar cell as in claim 2 above, wherein Chen et al. teaches forming the groove such that the portion of the bottom surface of the groove structure corresponding to the spacing region (14) is higher than the portion of the bottom surface of the groove structure that corresponds to the second region (13, see [0122]). As such, Chen et al. teaches the surface of the passivation layer (or 17/18 in the spacing region 14) adjacent to the substrate is lower than the surface of the doped amorphous silicon structure (16/30/28 in the second region 13) adjacent to the substrate along the preset direction. Regarding claim 6, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. teaches a surface of the tunneling oxide layer (29) adjacent to the substrate (11), a surface of the doped amorphous silicon structure (16/30/28) adjacent to the substrate (11), and a surface of the passivation layer (17/18) adjacent to the substrate (11) are flush with each other (see figs. 1-2). Regarding claim 7, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. teaches a surface of the substrate (11) in contact with the tunneling oxide layer (29), a surface of the substrate (11) in contact with the doped amorphous silicon structure (16/30/28), and a surface of the substrate (11) in contact with the passivation layer (17/18) are all polished surfaces (see figs. 1-2). Regarding claim 8, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. shows the surface of the substrate in the first doped region (12), the second doped region (13) and the insulating region (or the spacing region 14) are polished (see figs. 1-2). Chen et al. also teaches texturing the surface of at least one of the first regions, the second region and the insulating region (or the spacing region) to improve the light trapping effect of the surface of the corresponding regions (see [0126-0127]). Chen et al. does not show a surface of the substrate in contact with the tunneling oxide layer (in the first region) is a polished surface, and both of a surface of the substrate in contact with the doped amorphous silicon structure (in the second region) and a surface of the substrate in contact with the passivation layer (in the insulating region/spacing region) are textured surfaces in fig. 1. However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the solar cell in fig. 1 of Chen et al. by texturing both surfaces of the substrate in contact with the amorphous silicon structure (in the second region 13) and the passivation layer (in the insulating region/spacing region 14) such that a surface of the substrate in contact with the tunneling oxide layer (in the first region) is a polished surface, and both of a surface of the substrate in contact with the doped amorphous silicon structure (in the second region) and a surface of the substrate in contact with the passivation layer (in the insulating region/spacing region) are textured, because Chen et al. explicitly suggests texturing the second region (13) and the insulting region (14) to improve the light trapping effect of the surface of the regions (see [0126-0127]). Regarding claim 9, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. teaches a length in an extension direction of the insulating region (or spacing region 14) between the electrodes (fingers and busbar of opposite polarities) to be 200-700mm such as 200mm, 300mm (see [0232]). In other words, Chen et al. teaches a width of the insulating region (first and second dielectric layers) along an arrangement direction of the first doped region and the second doped region (or between the electrodes such as 27 and 28) to be 200mm or 300mm, which is within the claimed ranges from 150 μm to 300 μm. Regarding claim 10, Chen et al. disclose a solar cell as in claim 1 above, wherein Chen et al. teaches the insulating region comprising in a first dielectric layer (17) and a second dielectric layer (18, see figs. 1-2), texturing the insulating region (or the spacing region, see [0126-0127]), and textured surface is for anti-reflection to improve the photoelectric conversion efficiency by having light trapping effect (see claim col. 81, lines 26; col. 84, lines 12; col. 86, line 48; Fig. 2 and [0117]). Modified Chen et al. in claim 1 above does not teach arranging an anti-reflection layer on a side of passivation layer away from the substrate such that the passivation layer and the anti-reflection layer are not overlapped with the transparent conducting layer or the second transparent conducting layer along a thickness direction of the substate. Seo et al. discloses an insulating region (see gap insulation layer 160, figs. 1, 3K and 6) including a passivation layer (see layer 161 covering/protecting the substrate ’10, see figs. 1 and 3K) and an antireflective layer (see layer 162 having lower refractive index than layer 161, [0058], or the configuration of anti-reflection – reducing reflection of light entering the solar cell from the back), wherein the anti-reflection layer (162) is disposed on a side of the passivation layer (161) away from the substrate (110) such that the passivation layer (161) and the antireflection layer (162) are not overlapped with the first transparent conductive layer (133) and the second transparent conductive layer (143) along the thickness of the substrate (110, see figs. 1 and 3K). Seo et al. teaches such configuration of the insulating region (or the gap insulation 160) would improve efficiency of collection of carriers by preventing surface recombination of carriers generated by the semiconductor substrate (see [0038]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the solar cell of modified Chen et al. by forming the insulating region including the passivation layer and the antireflection layer as taught by Seo et al., because Seo et al. teaches such insulating region would improve efficiency of collection of carriers by preventing surface recombination of carriers generated by the semiconductor substrate. Regarding claims 11-12, modified Chen et al. discloses a solar cell according to claim 10, wherein Chen et al. teaches varying the thickness of the insulating region (17/18, see figs. 1-26 of Chen et al.) and Seo et al. discloses using an insulating region (160) of a passivation layer (161) and an antireflection layer (162) to improve efficiency of collection of carriers (see [0038] of Seo et al.). Modified Chen et al. does not explicitly teach a ratio of an overall thickness of the passivation layer and the anti-reflection layer to an overall thickness of the tunneling oxide layer, the doped polysilicon layer, and the first transparent conducting layer ranges from 1:1.3 to 1:2, nor do they teach a ratio of an overall thickness of the passivation layer and the anti-reflection layer to an overall thickness of the intrinsic hydrogenated amorphous silicon layer, the doped amorphous silicon layer, and the second transparent conducting layer ranges from 1:1.2 to 1:2. However, as the material cost and efficiency of the solar cell (or the efficiency of collection of carriers) are variables that can be modified, among others, by adjusting thicknesses of the insulating region (or the overall thickness passivation layer and the antireflection layer) and the first doped region (or the overall thickness of the tunneling oxide layer, the doped polysilicon and the first transparent conducting layer) and the second doped region (or the overall thickness of the intrinsic hydrogenated amorphous silicon layer, the doped amorphous silicon layer, and the second transparent conducting layer), the precise ratios of the insulating region to the first doped region and the insulating region to the second doped regions would have been considered a result effective variable by one having ordinary skill in the art at the time the invention was made. As such, without showing unexpected results, the claimed ratios cannot be considered critical. Accordingly, one of ordinary skill in the art at the time the invention was made would have optimized, by routine experimentation, the ratio of the insulating region to the first doped region and/or the ratio of the insulating region to the second doped region in the solar cell of modified Chen et al. to obtain the desired balance between the material cost and efficiency of the solar cell (In re Boesch, 617 F.2d. 272, 205 USPQ 215 (CCPA 1980)), since it has been held that where the general conditions of the claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. (In re Aller, 105 USPQ 223). Regarding claim 13, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. teaches a material of the tunneling oxide layer (or the first passivation layer 29) is silicon oxide (see [0183-0184], [0282]). Regarding claim 15, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen teaches the doped amorphous silicon layer is a doped amorphous silicon layer (see claim 1 above). Chen et al. does not disclose the amorphous silicon layer is a hydrogenated amorphous silicon layer (a-Si:H). Yamamoto et al. teaches using hydrogenated amorphous silicon with the dangling bond of the silicon atoms being terminated/passivated with hydrogen for amorphous silicon (see [0078]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the solar cell of modified Chen et al. by using hydrogenated amorphous silicon for the amorphous silicon as taught by Yamamoto et al., because Yamamoto et al. teaches hydrogenated amorphous silicon having silicon atoms being terminated/passivated with hydrogen (or better amorphous silicon). Such modification would involve nothing more than use of known material for its intended use in a known environment to accomplish entirely expected result. International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007). The Courts have held that the selection of a known material, which is based upon its suitability for the intended use, is within the ambit of one ordinary skill in the art. See In re Leshin, 125 USPQ 416 (CCPA 1960) (See MPEP 2144.07). Regarding claim 16, modified Chen et al. discloses a solar cell as in claim 1 above, wherein Chen et al. teaches a material of the passivation layer (17/18) is silicon oxide, aluminum oxide, silicon nitride, silicon carbide, or silicon oxynitride. Regarding claim 17, modified Chen et al. teaches a solar cell as in claim 1 above, wherein Chen et al. teaches a material of the substrate is an elemental semiconductor material (see silicon substrate or germanium substrate in paragraph [0115]), or a compound semiconductor material (see silicon germanium substrate in paragraph [0115]). Regarding claim 18, modified Chen et al. discloses a solar cell as in claim 10 above, wherein Seo et al. teaches using transparent conductive oxide (TCO) such as ITO or IZO for both the first transparent conducting layer and the second transparent conducting layer, or using the same transparent conductive oxide (TCO) films for both the first transparent conducting layer and the second transparent conducting layer. Regarding claim 19, modified Chen et al. discloses a solar cell as in claim 10 above, wherein Seo et al. shows the anti-reflection layer (162) is a single-layer structure (see figs. 1 and 3K). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over modified Chen et al. as applied to claim 1 above, and further in view of Swanson et al. (US 2006/0196535). Regarding claim 20, modified Chen et al. discloses a solar cell as in claim 1 above, and teaches a photovoltaic module including the back contact solar cell in claim 1 above (see [0082] and [0171]). Modified Chen et al. does not explicitly teach the photovoltaic module comprising a cell string formed by connecting a plurality of solar cells; an encapsulating adhesive film configured to cover a surface of the cell string; and a cover plate configured to cover a surface of the encapsulating adhesive film away from the cell string. Swanson et al. discloses a photovoltaic module (100) comprising a cell string formed by connecting a plurality of back contact solar cells (200, see figs. 1-2 and 7A), an encapsulating adhesive film (see 103 of EVA, figs. 1-2 and 7A, [0018]) and a cover plate (see transparent cover 104 of glass, figs. 1-2 and 7A) configured to cover a surface of the encapsulating adhesive film (103) on a side away from the cell string (200, see figs. 1-2 and 7A) so that the solar cells are protected to withstand environmental conditions and be used in the field (see figs. 1-2 and 7A, [0006-0008]) It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have used a plurality of connected back contact solar cells of Chen et al. to form a cell string and protecting the cell string in an encapsulating adhesive film and a cover plate covering a surface of the encapsulating adhesive film to form a photovoltaic module as taught by Swanson et al., because Chen et al. explicitly suggests forming a photovoltaic module and Swanson et al. teaches providing encapsulating adhesive film and the cover plate to protect the solar cells in the photovoltaic module. Response to Arguments Applicant’s arguments with respect to claim(s) 1- have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues Yamamoto does not teach using intrinsic hydrogenated amorphous silicon layer. Applicant points to [0088] of Applicant’s disclosure, which describes the intrinsic hydrogenated amorphous silicon layer serves to improve the contact performance. The examiner replies that Yamamoto is not relied upon for teaching intrinsic amorphous silicon layer. Chen et al. discloses the doped polysilicon passivation contact structure comprising an intrinsic amorphous silicon (see second passivation layer 30, [0104]; and also see [0186] which describes the material of the second passivation layer includes intrinsic amorphous silicon). Yamamoto teaches using intrinsic amorphous silicon for the passivation layer (or the layer 5 covering the substrate 1, see i-type non-single crystal film composed of i-type amorphous silicon described in [0063] of Yamamoto). In paragraph [0078], Yamamoto teaches “’Amorphous silicon’ herein encompasses also amorphous silicon in which dangling bond of a silicon atom is terminated with hydrogen, such as hydrogenated amorphous silicon”. In other words, Yamamoto explicitly teaches an intrinsic (or i-type) hydrogenated amorphous silicon layer, and hydrogenated amorphous silicon is expected to improve the performance of the contact and the solar cell, because hydrogenated amorphous silicon has the dangling bond (or a defect) is terminated with hydrogen – or the amorphous silicon with minimized defect. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH-TRUC TRINH whose telephone number is (571)272-6594. The examiner can normally be reached 9:00am - 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T. Barton can be reached at 5712721307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. THANH-TRUC TRINH Primary Examiner Art Unit 1726 /THANH TRUC TRINH/Primary Examiner, Art Unit 1726
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Prosecution Timeline

Apr 22, 2025
Application Filed
Jan 27, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §103 (current)

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