DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 6/1/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tavallaei et al. (US 2022/179780 A1) hereinafter Tavallaei et al.
Regarding claim 1, Tavallaei et al. teaches a processor-implemented method comprising:
determining whether a page usage of a first sub-memory region of a first memory node among a plurality of memory nodes of a memory is greater than or equal to a first threshold value (in a system having a plurality of nodes [0019], it is determined whether a retrieval condition is met, which may include a second measurement of the usage characteristic being above the usage threshold, e.g., the data may be initially accessed via bulk memory 306B Paragraph [0055]. Also see [0036]-[0041]);
determining a second sub-memory region of the first memory node in response to the page usage of the first sub-memory region being greater than or equal to the first threshold value (controller is configured to determine that data from a cold segment, determined via usage characteristic being below a predefined threshold Paragraph [0041], was paged out into expanded bulk memory and satisfies a retrieval condition, and to page the data back into extended memory Paragraph [0055]);
determining a target page among pages of the determined second sub-memory region; and allocating the determined target page of the second sub-memory region to the first sub-memory region (responsive to the retrieval condition being met, the data is paged back (i.e., allocated) into extended memory and the host memory address is re-mapped to the extended memory for efficient access Paragraphs [0044]-[0046, [0055]).
Regarding claim 2, Tavallaei et al. teaches all of the features with respect to claim 1 as outlined above.
Tavallaei et al. further teaches wherein the determining of the second sub-memory region of the first memory node in response to the page usage of the first sub-memory region being greater than or equal to the first threshold value comprises determining the second sub-memory region based on page usages of a plurality of sub-memory regions of the first memory node (usage characteristics for each memory segment is tracked in the segment table by maintaining timestamps/counters to indicate frequency of use and is used in assessing whether a memory segment is cold Paragraph [0044]).
Regarding claim 3, Tavallaei et al. teaches all of the features with respect to claim 1 as outlined above.
Tavallaei et al. further teaches wherein the allocating of the target page of the second sub-memory region to the first sub-memory region comprises associating a target physical address of the target page with a first sub-region identifier corresponding to the first sub-memory region (the plurality of mappings between host memory addresses and physical addresses of the pool is maintained in a segment table Paragraph [0044]-[0045], for example, when a segment is paged back to the extended memory, host memory address 314 is shown to be allocated via physical memory segment 320 Paragraph [0046] and identified via mapping of host addresses to physical addresses, and mapped offsets relative to reference host addresses to physical offsets Paragraph [0045]).
Claims 11 and 12 are rejected under 35 USC 102(a)(1) for the same reasons as claim 1, as outlined above.
Regarding claim 11, Tavallaei et al. teaches a non-transitory computer-readable storage medium storing code (storage machine including physical devices that execute software instructions by processors Paragraphs [0059]-[0061]) that, when executed by one or more processors, configures the one or more processors to perform the method of claim 1.
Regarding claim 12, Tavallaei et al. teaches an electronic device comprising: a memory comprising a plurality of memory nodes; and one or more processors configured to: perform the method of claim 1.
Regarding claim 13, Tavallaei et al. teaches all of the features with respect to claim 12 as outlined above.
Tavallaei et al. further teaches wherein the one or more processors comprise a first core associated with the first memory node, and the first core is configured to: perform the determining of whether the page usage of the first sub-memory region is greater than or equal to the first threshold value (in a system having a plurality of nodes [0019], it is determined whether a retrieval condition is met, which may include a second measurement of the usage characteristic being above the usage threshold, e.g., the data may be initially accessed via bulk memory 306B Paragraph [0055]. Also see [0036]-[0041]); and perform the determining of the second sub-memory region of the first memory node in response to the page usage of the first sub-memory region being greater than or equal to the first threshold value (controller is configured to determine that data from a cold segment, determined via usage characteristic being below a predefined threshold Paragraph [0041], was paged out into expanded bulk memory and satisfies a retrieval condition, and to page the data back into extended memory Paragraph [0055]).
Claim 14 is rejected under 35 USC 102(a)(1) for the same reasons as claim 3, as outlined above.
Allowable Subject Matter
Claims 4-10 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, “wherein the allocating of the target page of the second sub-memory region to the first sub-memory region comprises: changing a value of a first field indicating that a sub-memory region allocated to the target page within a bit field for the target physical address of the target page is changed to a preset value; and changing a value of a second field indicating a sub-memory region to be reallocated within the bit field for the target physical address of the target page to a value of the first sub-region identifier,” is not taught by the prior arts of record. The closest prior art is Tavallaei et al. in view of Zhu et al. (US 2026/0119075 A1). Zhu et al. teaches that a manner of mapping from a first area to a second area is to change a field that is in the physical address and that represents a row. For example, an address remapping module can modify a field of the physical address representing the row by performing an inversion on a fit in the field (e.g., ADDR’[x]). Thus, Zhu et al. generally teaches changing a value of a field within a physical address, however, is silent with regards to the remaining limitations of changing a value of a second field indicating a sub-memory region to be reallocated within the bit field for the target physical address of the target page to a value of the first sub-region identifier. Thus, the combination of Tavallaei et al. and Zhu et al. do not appear to teach the entirety of the claims. Claims 5-10 would be allowable at least due to its dependency on claim 4.
While one or more reasons are offered above citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Tavallaei et al. and Zhu et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Claim 15 recites substantially similar limitations as claim 4 and would therefore be allowable under the same rationale as claim 4. Claims 16-20 would be allowable at least due to its dependency on claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ammari et al. (US 2024/0311297) teaches identifying requests to allocate memory, and the memory can be represented via a node of a data structure to move pages based on its activity (i.e., hot or cold).
Wen et al. (US 2021/0157647 A1) teaches a non-uniform memory access system (NUMA) where latency can be reduced by monitoring which nodes are accessing which local memories, and migrating memory pages from the local memory of a first node to that of a different node.
Bennett et al. (US 2019/0138437 A1) teaches using performance counters to assign memory address ranges to different performance tiers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANE W BENNER whose telephone number is (571)270-0067. The examiner can normally be reached Mon - Thurs (8 AM - 5 PM).
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
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