DETAILED ACTION
This Office action is in response to the application filed on 22 April 2025. Claims 1-12 are currently pending and under examination. It is noted that while the present application has been filed as a divisional of 18/156,453, not all of the claims filed in the present application were restricted from the parent application as being directed to independent or distinct inventions (in this case, non-elected species inventions).
The status of the claims are as follows:
Claims 1 and 6 are drawn only to either generic subject matter or to subject matter that was part of the elected species of the parent application, and which was allowed and patented in the parent application. As such, they are not subject to the protections against double patenting rejections provided by 35 U.S.C. 121. Claims 1 and 6 have thus been rejected on the ground of non-statutory double patenting because they are anticipated by patented claims of the parent application. See below in this Office action.
Claims 2-5 and 7-10 are drawn to non-elected species that were subject to the final restriction requirement made in the parent application. As such, the prohibitions against double patenting rejections set forth in 35 U.S.C. 121 are applicable to claims 2-5 and 7-10.
Claims 11-12 are drawn to the elected species of the parent application, and include further subject matter that was not part of any allowed claim from the parent application. As such, while these claims are not entitled to protection from double patenting rejections under 35 U.S.C. 121, nonetheless no such rejection is made because they are patentably distinct from the patented claims from the parent application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/156,453, filed on 19 January 2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeuchi (US 2007/0145956).
In re claim 1, Takeuchi discloses a power supply system (Fig. 5), comprising:
a power factor correction converter circuit (3a), configured to correct a power factor of a rectified power to generate a first output power ([0043]: PFC circuit 3a receives and corrects power factor of the AC power from source 1 via the diode bridge 2, and generates first output power Vdc across C1), the power factor correction converter circuit comprising:
a boost power stage circuit (3a) comprising an inductor (L1) and a plurality of switches (Q1, D1) coupled to one another, the inductor is coupled between the rectified power (received from diode bridge 2) and a switching node (node between L1, Q1, and D1), the plurality of switches comprise a high-side switch (Fig. 5: D1) and a low-side switch (Q1), the high-side switch being coupled between the switching node (node between L1, Q1, and D1) and the first output power (Vdc), and the low-side switch (Q1) being coupled between the switching node and a ground potential (See Fig. 5); and
a power factor correction control circuit (32a), configured to control at least one of the switches to switch the inductor to convert the rectified power to generate the first output power ([0043], [0045]);
an isolated power converter circuit (4a, 31), configured to convert the first output power to generate a second output power ([0044]: isolated converter 4a converts Vdc to second output power at load 5), the isolated power converter circuit comprising (see detailed embodiments shown in Figs. 16 or 17):
a transformer (Figs. 16, 17: T1) comprising a primary winding (P1), a secondary winding (S1), and an auxiliary winding (P2) coupled to one another (via the transformer core as illustrated), the auxiliary winding is configured to generate an auxiliary voltage (voltage at the terminal labeled “to PFC on-off circuit in Figs. 16, 17) relevant to the second output power (at least by virtue of being generated by the same circuitry via the switching of Q2 in the known and conventional manner; see [0052], [0089], [0090]);
wherein when the auxiliary voltage is lower than a disable threshold (see, e.g., Fig. 8: auxiliary voltage from load detection circuit is compared to a disable threshold by 342: [0055]-[0056]), the power factor correction control circuit controls the high-side switch to be ON and the low-side switch to be OFF to provide a bypassing connection from the rectified power to the first output power and stop correcting the power factor of the rectified power (Abstract, [0008], [0012], [0053], [0088]-[0090]: when the PFC control circuit is deactivated, Q1 is understood to be turned OFF (switching is stopped) by virtue of its being a depletion mode NMOS transistor as depicted; high side switch D1 is thus controlled to be turned ON by Q1 being held off by virtue of the relative voltage magnitudes at its anode and cathode, and the bypass connection is provided via inductor L1 and diode D1).
In re claim 3, Takeuchi discloses an auxiliary diode (Fig. 16: D9), configured to rectify the auxiliary voltage (voltage from P2) to generate a rectified auxiliary voltage (at anode of D9); and
an auxiliary capacitor (C5), configured to filter the rectified auxiliary voltage (Fig. 16: C5 forms low pass filter of rectified voltage from D9);
wherein or (it is noted that the broadest reasonable interpretation of “and/or” is “or”), the power factor correction control circuit determines whether the auxiliary voltage is lower than the disable threshold according to the rectified auxiliary voltage (see, e.g., Fig. 8: auxiliary voltage from load detection circuit is compared to a disable threshold by 342: [0055]-[0056]).
In re claim 4, Takeuchi discloses a voltage divider circuit (Fig. 17: R28/R29) configured to divide the auxiliary voltage to generate a sensed voltage (R28/R29 divide voltage from aux winding P2 to generate sensed voltage at “TO PFC ON-OFF CONTROL CIRCUIT”), wherein the power factor correction control circuit determines whether the auxiliary voltage is lower than the disable threshold according to the sensed voltage (see, e.g., Fig. 8: auxiliary voltage from load detection circuit is compared to a disable threshold by 342: [0055]-[0056]).
In re claim 6, Takeuchi discloses wherein the power factor correction control circuit determines whether the auxiliary voltage is lower than the disable threshold after a delay time from a rising edge of the auxiliary voltage (Fig. 16: for instance, according to the time constant as set by the filter circuit formed by R9, C5 in the load detection circuit 31a, as the circuit functionality is understood based on the diagram and descriptions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Kim et al. (US 2021/0249950; hereinafter “Kim”).
In re claim 2, Takeuchi discloses the invention according to claim 1 as explained above, including bypassing the PFC converter when the auxiliary voltage is lower than the disable threshold (see, e.g., Fig. 8: auxiliary voltage from load detection circuit is compared to a disable threshold by 342: [0055]-[0056]).
However, Takeuchi does not disclose wherein the boost power stage circuit further comprises a bypass switch coupled between the rectified power and the first output power, and the power factor correction control circuit controls the bypass switch to be ON to provide the bypassing connection from the rectified power to the first output power and stop correcting the power factor of the rectified power.
Whereas Kim discloses a power supply system with a PFC converter (see Figs. 11-12: PFC 200) including a bypass switch (212) connected between the input and output of the PFC converter (200) and the control circuit controls the bypass switch to be ON to provide a bypassed connection and stop the PFC converter ([0111]-[0114]) in order to improve efficiency at light load ([0005]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Takeuchi by providing a bypass switch coupled between the rectified power and the first output power as shown by Kim), and wherein when the auxiliary voltage is lower than the disable threshold, the power factor correction control circuit controls the bypass switch to be ON to provide the bypassing connection from the rectified power to the first output power and stop correcting the power factor of the rectified power, in order to improve system efficiency at light load as Kim teaches.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Nate et al. (US 2020/0251991; hereinafter “Nate”).
In re claim 5, Takeuchi discloses the invention according to claim 1 as explained above, but does not further disclose wherein the power factor correction control circuit further comprising a sample-and-hold circuit configured to sample and hold the auxiliary voltage at a falling edge to generate an auxiliary sample-and-hold voltage, wherein the power factor correction control circuit determines whether the auxiliary voltage is lower than the disable threshold according to the auxiliary sample-and-hold voltage.
Whereas Nate discloses an isolated power converter (Fig. 3) and its controller (100y; Fig. 4) which includes a sample and hold circuit (Fig. 4: 122) to sample the auxiliary voltage (Fig. 4: Vp at terminal T15; c.f. Fig. 3) at a falling edge (as understood from [0099]-[0100]: to sample the voltage corresponding to the output voltage, the auxiliary voltage must be sampled at the falling edge, commonly called the “knee-point” of the waveform) in order to obtain feedback with reduced standby power consumption and good noise tolerance ([0098], [0101). Further, it is common knowledge in the art that a further advantage of obtaining feedback from the auxiliary winding is that it avoids the need to pass a feedback signal back from the output across the galvanic isolation barrier.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Takeuchi by providing a sample-and-hold circuit as shown by Nate, configured to sample and hold the auxiliary voltage at a falling edge to generate an auxiliary sample-and-hold voltage, wherein the power factor correction control circuit determines whether the auxiliary voltage is lower than the disable threshold according to the auxiliary sample-and-hold voltage in order to obtain feedback with reduced standby power consumption and good noise tolerance, as well as to avoid the need to obtain a feedback signal from the secondary side across the galvanic isolation barrier of the converter.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi.
In re claims 7-9, Takeuchi discloses the invention according to claim 1 as explained above, but does not further disclose that the isolated power converter circuit is an asymmetrical half-bridge flyback power converter, a half-bridge inductor-inductor-capacitor (LLC) flyback power converter, or a full-bridge inductor-inductor-capacitor (LLC) flyback power converter.
However, these were three very commonly used topologies of isolated power converter, and since Takeuchi’s disclosure is not limited to only being of use to a single, particular topology, it would be a routine practice and well within the ability one of ordinary skill in the art to select an appropriate topology from a set of known alternatives according to the needs or specifications of a certain usage scenario. For instance, according to the common knowledge of the art, one might select an asymmetrical half-bridge flyback converter for its high efficiency across a range of load powers and relatively simple control structure; one may choose a half-bridge or full-bridge LLC resonant converter for its soft-switching ability that enables high efficiency especially at higher load powers and across a narrower load range.
Therefore it would have been obvious to try, for one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the system of Takeuchi by using it with alternative topologies of the isolated power converter, including an asymmetrical half-bridge flyback power converter, a half-bridge inductor-inductor-capacitor (LLC) flyback power converter, or a full-bridge inductor-inductor-capacitor (LLC) flyback power converter according to the known trade-offs associated with each topology, in order to obtain an optimum design in a given usage scenario.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Lin et al. (US 2017/0366088; hereinafter “Lin”).
In re claim 10, Takeuchi discloses the invention according to claim 1 as explained above, including the power supply system, power factor correction converter circuit, isolated power converter circuit, and detection circuit, as well as the functionality of stopping the PFC operation according to the disable signal (see citations provided for corresponding limitations from claim 1, above in this Office action). However, Takeuchi does not disclose an optocoupler circuit coupled between a secondary side of the isolated power converter circuit and the power factor correction converter circuit; wherein the disable signal is transmitted via the optocoupler circuit.
Whereas Lin discloses an isolated power converter (Fig. 2) that uses an opto-coupler (164; see Figs. 3-4) in a conventional manner to provide feedback signals related to the output power provided to the load from the secondary side to the primary side while maintaining galvanic isolation ([0035]), which is done for safety and for regulatory reasons.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Takeuchi by including an optocoupler circuit coupled between a secondary side of the isolated power converter circuit and the power factor correction converter circuit as shown by Lin; wherein the disable signal is transmitted via the optocoupler circuit, in order to provide the necessary feedback signals while maintaining the galvanic isolation between primary and secondary sides, as needed for safety and regulatory reasons.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12,381,470.
Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of claims 1 and 6 of the instant application are recited in corresponding claims of the patent. Thus, in effect, claims 1 and 6 are anticipated the previously patented claims.
All of the limitations of claim 1 of this application are recited in or required by claim 3 of the patent. All of the limitations of claim 6 of this application are recited in or required by claim 4 of the patent.
Furthermore, although the claims under rejection are being presented in a divisional application ostensibly filed pursuant to a restriction requirement made in the parent application 18/156,453, the provisions of 35 U.S.C. 121 protecting against such rejection are not applicable to these claims. As was stated in the Notice of Allowance mailed on 14 May 2025:
Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
That is the case in the present application, where independent claim 1 and dependent claim 6 are both drawn to a generic embodiment of the invention instead of being limited to a non-elected species of the maintained restriction requirement. This is evidenced by the fact that claims 1 and 6 are anticipated by the allowed (and now patented) claims 3 and 4, respectively, of the parent application.
Allowable Subject Matter
Claims 11-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 11-12, the closest prior art in Takeuchi fails to disclose or suggest the power supply system as a whole, including in which the isolated power converter circuit complies with a power supply specification, so that the second output power has an output current upper limit, wherein the output voltage threshold is calculated from the output power threshold and the output current upper limit; and wherein when the power supply system and a load device are coupled to each other through a bus, the bus control circuit adjusts the voltage of the second output power according to at least one command sent by the load device through the bus as recited in claim 11.
Conclusion
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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