DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 57-58, 63, 81-83 are rejected under 35 U.S.C. 102(a)(2) as being anticipated Loh et al (US 20260178507, Loh).
As to claim 57, Loh discloses an apparatus (fig. 2) comprising:
interface circuitry (fig. 1 interface 112, par. 48);
machine readable instructions (OS 104); and
control circuitry (CPU 102) to at least one of instantiate or execute the machine readable instructions to:
categorize a workload (par. 95) as memory-intense or compute-intense (“whether the applications memory intensive” or “compute-intensive”); and
based on the categorization, selectively couple (par. 95) programmable circuitry (processor core 204) to main memory (main memory 106) via a L1 cache (memory architecture 218) and a L2 cache or via buffer circuitry (memory architecture 228).
As to claim 58, Loh discloses the apparatus of claim 57, wherein the wherein the instructions cause the control circuitry to couple the programmable circuitry to the main memory via the L1 cache and the L2 cache based on the categorization of the workload as compute-intense (par. 95).
As to claim 63, Loh discloses the apparatus of claim 57, wherein the instructions cause the control circuitry to categorize the workload as memory-intense if the workload corresponds to training a machine learning model, executing a machine learning model, graphics rendering, or high performance computing applications (par. 95).
As to claims 81-82, all the same elements of claims 57-58 are listed but in mean-for function form. Therefore, the supporting rationale of the rejection to claims 57-58 applies equally to claims 81-82.
As to claims 83, Loh discloses the apparatus of claim 81, wherein the controlling means is to couple the implementing means to the storage means via the second means for data or instruction transfer based on the categorization of the workload as memory-intense (par. 95).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 59 is rejected under 35 U.S.C. 103 as being unpatentable over Loh in view of Subramanian et al (US 20200218605, Subramanian).
As to claim 59, Loh discloses the apparatus of claim 57, but does not disclose the limitations in claim 59. In the same field of art (data processing), Subramanian discloses a storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system (abstract). In one embodiment, Subramanian further discloses a programmable circuitry (host system 105) to a main memory (device 120) via a buffer circuitry (HMB 212) based on the categorization of the workload as memory-intense (par 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Loh and Subramanian, by comprising the instructions to cause the control circuitry to couple the programmable circuitry to the main memory via the buffer circuitry based on the categorization of the workload as memory-intense. The motivation is to reduce the cost of the system (par. 3).
Claim 60-61 are rejected under 35 U.S.C. 103 as being obvious over Loh in view of Manne et al (US 20260119278, Manne).
As to claim 60, Loh discloses the apparatus of claim 57 but does not disclose the limitations in claim 60. In the same field of art (data processing), Manne discloses a system includes a plurality of compute nodes including a management node and a plurality of execution nodes (abstract). In one embodiment, Manne discloses wherein the instructions cause a control circuitry to:
estimate an amount of data reusage in the workload (par. 93, “amount of memory usage”); and
categorize the workload as compute-intense if the amount of data reusage satisfies a threshold (par. 98 “at least a threshold amount of processing resources”); and
categorize the workload as memory-intense if the amount of data reusage fails to satisfy the threshold (par. 93 “threshold amount of memory resources”. Note: The threshold is the combination of the processing threshold and the memory threshold).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Loh and Manne, by comprising the instructions to cause the control circuitry to:
estimate an amount of data reusage in the workload; and
categorize the workload as compute-intense if the amount of data reusage satisfies a threshold; and
categorize the workload as memory-intense if the amount of data reusage fails to satisfy the threshold.
The motivation is to improve the efficiency and reliability of the system (par. 1).
As to claim 61, Loh/Manne discloses the apparatus of claim 60, wherein the instructions cause the control circuitry to estimate the amount of data reusage by performing a static code analysis (Manne, fig. 3).
Claim 64 is rejected under 35 U.S.C. 103 as being obvious over Loh in view of Benisty et al (US 20250117037, Benisty).
As to claim 64, Loh discloses the apparatus of claim 57 but does not disclose the limitations in claim 64. In the same field of art (data processing), Benisty discloses instructions cause a control circuitry to categorize the workload as a read-workload or a write-workload. (par 32-33). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Loh and Benisty, by comprising the instructions cause the control circuitry to categorize the workload as a read-workload or a write-workload. The motivation is to improve the performance of the system (par. 3).
Claim 89 is rejected under 35 U.S.C. 103 as being unpatentable over Loh in view of Zuravleff et al (US 5812799, Zuravleff).
As to claim 89, Loh discloses the apparatus of claim 44, but does not disclose the limitations in claim 89. In the same field of art (data processing), Zuravleff discloses a non-blocking load buffer for use in a high-speed microprocessor and memory system (abstract). Zuravleff further discloses an implementing means (fig. 4 processor 30) is to read data from a second means (buffer 10) for data or instruction transfer in a First In First Out (FIFO) manner (FIFO 116). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Loh and Zuravleff, by comprising, after the controlling means couples the implementing means to the storage means via the second means for data or instruction transfer, the implementing means to read data from the second means for data or instruction transfer in a First In First Out (FIFO) manner. The motivation is to improve the performance of the system (col 3 ln 43-50).
Claims 1-3, 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Publication (CPU cache, December 30, 2018, Pub1).
As to claim 1, Zuravleff discloses an apparatus to access memory (fig. 4), the apparatus comprising:
main memory (device 50, col 5 ln 45-51);
a cache in circuit with the main memory (cache 20);
buffer circuitry in circuit with the main memory (buffer 10, fig. 5 return queue 116)
control circuitry (fig. 10, control 510) to cause delivery of data to programmable circuitry (processor 30) through the buffer circuitry without writing to the cache (col 5 lns 35-40).
Zuravleff does not disclose a L1 cache and a L2 cache as claimed. However, configuring cache levels would have been well-known to one of ordinary skill in the art at the invention time. For instance, Pub1 discloses a CPU cache comprises a L1 cache and a L2 cache (par 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff and Pub1, by comprising a L1 cache and a L2 cache in circuit with the the main memory and the control circuitry to cause delivery of data to programmable circuitry through the buffer circuitry without writing to either of the L1 cache or the L2 cache. The motivation is to improve the performance of the system (par. 1).
As to claim 2, Zuravleff/Pub1 discloses the apparatus of claim 1, wherein the control circuitry is to:
couple the programmable circuitry to the main memory via the buffer circuitry (Zuravleff, col 5 lns 35-40); and
after the coupling, instruct the main memory to write data to the buffer circuitry (col 7, 1-5).
As to claim 3, Zuravleff/Pub1 discloses the apparatus of claim 2, wherein after the control circuitry couples the programmable circuitry to the main memory via the buffer circuitry, the programmable circuitry is to read the data from the buffer circuitry in a First In First Out (FIFO) manner (Zuravleff, col 7 ln 1-5).
As to claim 43, Zuravleff discloses an apparatus (fig. 4) comprising:
means for storing data or instructions (device 50, col 5 ln 45-51);
first means for data or instruction transfer in circuit with the storage means (cache 20), the first means for data or instruction transfer including a cache;
second means for data or instruction transfer in circuit with the storage means (buffer 10);
means for implementing a workload (processors 30); and
controlling means (fig. 10, control 510) to cause delivery of data to the implementing means through the second means for data or instruction transfer without writing to the cache (col 5 lns 35-40).
Zuravleff does not disclose a L1 cache and a L2 cache as claimed. However, configuring cache levels would have been well-known to one of ordinary skill in the art at the invention time. For instance, Pub1 discloses a CPU cache comprises a L1 cache and a L2 cache (par 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff and Pub1, by configuring the first means for data or instruction transfer including an L1 cache and an L2 cache and controlling means to cause delivery of data to the implementing means through the first means for data or instruction transfer or through the second means for data or instruction transfer without writing to either of the L1 cache or the L2 cache. The motivation is to improve the performance of the system (par. 1).
As to claim 44, all the same elements of claim 2 are listed but in mean-for function form. Therefore, the supporting rationale of the rejection to claim 2 applies equally to claim 44.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1 and further in view of Chen (US 20110128595).
As to claim 4, Zuravleff/Pub1 discloses the apparatus of claim 3, but does not disclose the limitations in claim 4. In the same field of art (data processing), Chen discloses a scanning speed adjusting method is used in a scanning system including a scanning module and a controller (abstract). In one embodiment, Chen discloses a speed at which data is writen to a buffer circuitry and a speed at which data is read data from the buffer circuitry be different (par 22). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1 and Chen, by configuring a speed at which the main memory writes data to the buffer circuitry and a speed at which the programmable circuitry reads data from the buffer circuitry be different. The motivation is to improve the efficiency of the system (par. 6).
Claims 5-6, 47-48 are rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1 and further in view of Walker et al (US 20190179757).
As to claim 5, Zuravleff/Pub1 discloses the apparatus of claim 2, but does not disclose the limitations in claim 5. In the same field of art (data processing), Walker discloses a processing system including an interconnect fabric coupled to a local memory and at least one compute cluster coupled to the interconnect fabric (abstract). In one embodiment, Walker further discloses the step of coupling a second programmable circuitry (fig. 1 one of cores 114-117) to the main memory via L1 cache and the L2 cache (cache 118) and instruct a main memory to write second data to the L1 cache or L2 cache (par. 11 “load data from the local memory”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1 and Walker, by including the data as first data, the programmable circuitry as first programmable circuitry, and including second programmable circuitry, the control circuitry to: couple the second programmable circuitry to the main memory via L1 cache and the L2 cache; and instruct the main memory to write second data to the L1 cache or L2 cache. x. The motivation is to improve the performance of the system (par. 1).
As to claim 6, Zuravleff/Pub1/Walker discloses the apparatus of claim 5, wherein the first programmable circuitry is to read the first data through the buffer circuitry and the second programmable circuitry is to read the second data through the L1 cache and the L2 cache concurrently (Walker, par. 25).
As to claims 47-48, all the same elements of claims 5-6 are listed but in mean-for function form. Therefore, the supporting rationale of the rejection to claims 5-6 applies equally to claims 47-48.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1 and further in view of Lotlikar et al (US 12458629, Lotlikar).
As to claim 8, Zuravleff/Pub1 discloses the apparatus of claim 1, but does not disclose the limitations in claim 8. In the same field of art (data processing), Lotlikar discloses a Network On a Chip (NOC) and a main memory in circuit with both the L1 cache and the L2 cache (fig. 1b, col 3 ln 11-30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1 and Lotlikar in order to improve the functionality of the system (col 3 ln 11-30).
Claims 9, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1 and further in view of Chang et al (US 20180157435, Chang).
As to claim 9, Zuravleff/Pub1 discloses the apparatus of claim 1, but does not disclose the limitations in claim 9. In the same field of art (data processing), Chang discloses methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance (abstract). In one embodiment, Chang discloses a switch circuitry (fig. 1 interconnect 134), the control circuitry to selectively couple a programmable circuitry (core 106) to the main memory (main memory 114) by changing a state of the switch circuitry (par. 28). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1 and Chang, by including switch circuitry, the control circuitry to selectively couple the programmable circuitry to the main memory by changing a state of the switch circuitry. The motivation is to improve the performance of the system (par. 4).
As to claim 12, Zuravleff/Pub1/Chang discloses the apparatus of claim 9, wherein:
the buffer circuitry is input buffer circuitry (Zuravleff, buffer 10);
the switch circuitry is input switch circuitry (Chang, switch 134);
the apparatus includes output buffer circuitry and output switch circuitry (fig. 1);
the control circuitry to:
control the output switch circuitry to couple the programmable circuitry to the main memory via the output buffer circuitry (par. 28); and
instruct the programmable circuitry to write data to the output buffer circuitry (Zuravleff, col 5 lns 35-40).
Claims 13, 55 are rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1 and further in view of Tan (US 20180357006).
As to claim 13, Zuravleff/Pub1 discloses the apparatus of claim 1 but does not disclose the limitations in claim 13. In the same field of art (data processing), Tan discloses a buffer allocation method (abstract). In one embodiment, Tan further discloses a control circuitry (fig. 7) is to:
instruct a main memory to write first data to a cache (par. 64 “cached buffer object”);
based on a metric associated with the cache (cached or non-cache buffer object):
decouple the programmable circuitry from the cache and recouple the programmable circuitry to a buffer circuitry (par. 64, “non-cached buffer object”); and
instruct the main memory to write second data to the buffer circuitry (par. 64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1 and Tan, by comprising the control circuitry to:
instruct the main memory to write first data to the L2 cache;
based on a metric associated with the L1 cache and the L2 cache:
decouple the programmable circuitry from the L1 cache and recouple the programmable circuitry to the buffer circuitry; and
instruct the main memory to write second data to the buffer circuitry.
The motivation is to reduce the time and cost of the system (abstract).
As to claim 55, all the same elements of claim 13 are listed but in mean-for function form. Therefore, the supporting rationale of the rejection to claim 13 applies equally to claim 55.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zuravleff in view of Pub1/Tan and further in view of Rohillah et al (US 11886354, Rohillah).
As to claim 14, Zuravleff/Pub1 discloses the apparatus of claim 13 but does not disclose the limitations in claim 14. In the same field of art (data processing), Rohillah discloses a control circuitry is to determine the metric of the L1 cache and the L2 cache by: comparing a cache hit rate of a first level the L1 cache to a first threshold; or comparing a cache hit rate of a second level the L2 cache to a second threshold (col 3 ln 58-65). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zuravleff/Pub1/Tan and Rohillah, by configuring the control circuitry to determine the metric of the L1 cache and the L2 cache by: comparing a cache hit rate of a first level the L1 cache to a first threshold; or comparing a cache hit rate of a second level the L2 cache to a second threshold. x. The motivation is to improve the performance of the system (col 1 ln 20-27).
Allowable Subject Matter
Claim 10-11, 62 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
