NON-FINAL OFFICE ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,391,638 to Metuki in view of U.S. Patent Pub. No. 20150143200 to Chinnakkonda Vidyapoornachary et al. (hereinafter Chinnakkonda).
Metuki discloses:
1. A method for providing a fault flag of a semiconductor memory device, comprising:
storing a fault flag of the semiconductor memory device (col. 3, lns. 21-33);
inserting the fault flag into a metadata field of a data packet of the semiconductor memory device (col. 3, lns. 21-33); and
outputting the data packet (col. 3, lns. 21-33).
Metuki does not disclose expressly changing an operation mode of the semiconductor memory device from a meta mode to a Reliability, Availability and Serviceability (RAS) mode.
Chinnakkonda teaches changing an operation mode of the semiconductor memory device from a meta mode to a Reliability, Availability and Serviceability (RAS) mode (paras. [0026], [0030]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Metuki by changing an operation mode, as taught by Chinnakkonda. A person of ordinary skill in the art would have been motivated to do so in order to enable independent ECC capability per DRAM device, as discussed by Chinnakkonda (para. [0027]).
Modified Metuki discloses:
2. The method of claim 1, wherein the fault flag includes at least one of a valid read operation flag, an On Die Error Correcting Code Correctable Error flag, an On Die Error Correction Code Uncorrectable Error flag, or a Link-Error Correction Code Uncorrectable Error Poison flag (col. 3, lns. 21-33).
Claims 9 and 11 are a semiconductor memory device for performing the identical steps as recited by the method of claims 1 and 2, and are rejected under the same rationale.
Claims 3-8, 10, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Metuki in view of Chinnakkonda, and further in view of U.S. Patent Pub. No. 2020/0394103 to Schaefer et al. (hereinafter Schaefer).
Metuki discloses
3. The method of claim 1, wherein inserting the fault flag into the metadata field comprises writing a bit value (col. 2, lns. 55-58 and Fig. 2A).
However, Metuki does not disclose expressly wherein inserting the fault flag into the metadata field comprises repeatedly writing a bit value.
Schaefer teaches wherein inserting the fault flag into the metadata field comprises repeatedly writing a bit value (paras. [0081], [0089]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Metuki by repeatedly writing a bit value as a fault flag, as taught by Schaefer. A person of ordinary skill in the art would have been motivated to do so in order to allow for more redundancy and protect against bit errors in the fault flag.
Modified Metuki discloses:
4. The method of claim 3, comprising identifying the fault flag by a majority decision method for the repeatedly written bit value (Schaefer - paras. [0081], [0089]).
5. The method of claim 1, comprising activating a link Error Correcting Code (ECC) mode in the semiconductor memory device in the RAS mode (Schaefer - para. [0089]).
6. The method of claim 5, comprising generating a link ECC parity in the semiconductor memory device (Schaefer - para. [0089]).
7. The method of claim 6, comprising inserting the link ECC parity into a link ECC field of the data packet (Schaefer - para. [0089]).
8. The method of claim 7, comprising detecting or correcting a fault using the fault flag or the link ECC parity (Schaefer - paras. [0081], [0089]).
Claims 10 and 12-14 are a semiconductor memory device for performing the identical steps as recited by the method of claims 3 and 5-7, and are rejected under the same rationale.
Claims 15-20 are a method for performing the identical steps as recited by the method of claims 3, 4, and 5-8, and are rejected under the same rationale.
Conclusion
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/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
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