DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Patent application filed on 4/22/2025.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 3/16/2022.
Drawings
The Examiner contends that the drawings submitted on 4/22/2025 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,299,484 in view of Nield et al. (U.S. 2020/0073713), in view of Volos et al. (U.S. 2020/0110676), in view of Official Notice.
Instant Application
U.S. Patent No. 12,299,484
1. A dispatch engine apparatus configured as an integrated circuit (IC) for an AI accelerator IC, the apparatus comprising:
14. A chiplet device, the device comprising:
a plurality of tiles, each of the tiles comprising a plurality of slices, a central processing unit (CPU) coupled to the plurality of slices, and a dispatch engine device coupled to the CPU; wherein the dispatch engine device comprises:
a task queue module comprising
a task queue module
a plurality of rows, numbered from 1 to N;
a plurality of columns numbered from 1 to M;
where each of N and M is an integer greater than 4; and
a plurality of cells, each of the cells being defined by one of the plurality of rows and one of the plurality of columns;
a task queue module having a plurality of cells,
wherein the task queue module is configured to receive one or more task groups, each of the task groups having a plurality of work units configured in a hierarchy of queues; and wherein the task queue module is configured to store each of the plurality of work units of each task group in one of the plurality of cells such that the plurality of work units of each task group is stored according to the hierarchy of queues;
the task queue module being configured to receive one or more task groups, each of the task groups having a plurality of work units configured in a hierarchy of queues, and wherein the task queue module is configured to store each of the plurality of work units of each task group in one of the plurality of cells such that the plurality of work units of each task group are stored according to the hierarchy of queues;
a completion handler module coupled between a plurality of destination devices and each of the plurality of cells in the task queue module, and configured to send a completion signal upon a completion condition to update a status of one or more of the plurality of cells;
a completion handler module coupled between the plurality of slices and each of the plurality of cells in the task queue module and configured to send a completion signal upon a completion condition to update a status of one or more of the plurality of cells;
wherein the plurality of destination devices are configured within one or more chiplet devices of the AI accelerator IC;
a resource monitor module coupled to each of the plurality of cells in the task queue module and configured to monitor a state of each of the plurality of destination devices; and
a resource monitor module coupled to each of the plurality of cells in the task queue module and configured to monitor a state of each of the slices; and
a task dispatcher module coupled to each of the plurality of cells in the task queue module and configured to asynchronously dispatch the work unit stored in each of the plurality of cells to one of the plurality of destination devices in a parallel pipeline process using a bus device coupled to the task queue module such that each cell is configured to communicate through the bus device to one of the plurality of destination devices.
a task dispatcher module coupled to each of the plurality of cells in the task queue module and configured to asynchronously dispatch the work unit stored in each of the plurality of cells to one of the plurality of slices in a parallel pipeline process using the bus device; a bus device coupled between the plurality of cells in the task queue module and the plurality of slices such that each cell is configured to communicate through the bus device to one of the plurality of slices;
a plurality of die-to-die (D2D) interconnects coupled to each of the CPUs in each of the tiles; a peripheral component interconnect express (PCIe) bus coupled to the CPUs in each of the tiles;a dynamic random access memory (DRAM) interface coupled to the CPU in each of the tiles; anda global CPU interface coupled to each of the CPUs in each of the plurality of tiles.
Additionally, Nield disclosed:
a task queue module (Nield: Figure 1 element 108, paragraph 35) comprising
a plurality of rows, numbered from 1 to N (Nield: Figure 1 elements 112-114, paragraph 39);
a plurality of columns numbered from 1 to M (Nield: Figure 1 elements 112, 116-124, paragraph 39);
where each of N and M is an integer greater than 4 (Nield: Figure 1 elements 112-124, paragraph 39)(The number of rows and columns in the task queue are each greater than 4.); and
a plurality of cells, each of the cells being defined by one of the plurality of rows and one of the plurality of columns (Nield: Figure 1 elements 112-124, paragraph 39)(The various storage elements of the task queue read upon the plurality of cells.);
wherein the plurality of destination devices are configured within one or more chiplet devices of the AI accelerator IC (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraphs 35 and 38)(The broadest reasonable interpretation of a chiplet device is processing logic that is configured to perform parallel operations. Volos disclosed multiple compute nodes (i.e. destination devices) to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. The set of compute nodes reads upon a chiplet device. Additionally, official notice is given that compute nodes can implement multiple processing blocks for the advantage of parallel execution. Thus, it would have been obvious to implement the compute nodes of Volos within Nield that each perform parallel operations.).
a CPU coupled to the plurality of destination devices via a crossbar device (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraphs 35 and 38)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. Official notice is given that processing systems can include CPUs for the advantage of performing general processing tasks. Thus, it would have been obvious to one of ordinary skill in the art to implement a CPU in the combination. Additionally, official notice is given that crossbars can be used to connect processing elements together for the advantage of sharing and communicating data. Thus, it would have been obvious to one of ordinary skill in the art to implement a crossbar to connect the CPU to the compute nodes.).
Claims 14 and 20 are similar to claim 1 and are rejected for the same reasons. The limitations not shown by the claims in U.S. Patent No. 12,299,484 are read upon as specified by the rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nield et al. (U.S. 2020/0073713), in view of Volos et al. (U.S. 2020/0110676), in view of Tanaka et al. (U.S. 2002/0087611), in view of Official Notice.
As per claim 1:
Nield and Volos disclosed a dispatch engine apparatus configured as an integrated circuit (IC) for an Al accelerator IC, the apparatus comprising:
a task queue module (Nield: Figure 1 element 108, paragraph 35) comprising
a plurality of rows, numbered from 1 to N (Nield: Figure 1 elements 112-114, paragraph 39);
a plurality of columns numbered from 1 to M (Nield: Figure 1 elements 112, 116-124, paragraph 39);
where each of N and M is an integer greater than 4 (Nield: Figure 1 elements 112-124, paragraph 39)(The number of rows and columns in the task queue are each greater than 4.); and
a plurality of cells, each of the cells being defined by one of the plurality of rows and one of the plurality of columns (Nield: Figure 1 elements 112-124, paragraph 39)(The various storage elements of the task queue read upon the plurality of cells.);
wherein the task queue module is configured to receive one or more task groups, each of the task groups having a plurality of work units configured in a hierarchy of queues (Volos: Figure 4, paragraphs 29 and 35-36)(Nield: Figures 1 and 3 elements 108-110, 120, and 302-304, paragraphs 35-36, 39-40, and 44-45)(Nield disclosed receiving indications of task dependency completions, but doesn’t explicitly state that such completions include other tasks. Volos disclosed tasksets (i.e. task groups) that include a group of tasks to be performed. The combination allows for Nield to receive tasks that are part of a taskset and set dependencies between tasks. Setting dependencies between tasks allows for a hierarchy of stored tasks within the task queue.); and wherein the task queue module is configured to store each of the plurality of work units of each task group in one of the plurality of cells such that the plurality of work units of each task group is stored according to the hierarchy of queues (Volos: Figure 4, paragraphs 29 and 35-36)(Nield: Figures 1 and 3 elements 108-110, 120, and 302-304, paragraphs 35-36, 39-40, and 44-45)(The combination allows for Nield to receive tasks that are part of a taskset and set dependencies between tasks. The receives tasks that are part of tasksets are stored within the task queue storage elements. Setting dependencies between tasks allows for a hierarchy of stored tasks within the task queue.);
a completion handler module coupled between a plurality of destination devices and each of the plurality of cells in the task queue module, and configured to send a completion signal upon a completion condition to update a status of one or more of the plurality of cells (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 5A-B elements 104, 108, and 502, paragraphs 35, 38, and 55-56)(The logic that generates an indication that a task has been completed reads upon the completion handler. Nield disclosed a single processing block for executing scheduled tasks. Volos disclosed multiple compute nodes (i.e. destination devices) to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks.);
wherein the plurality of destination devices are configured within one or more chiplet devices of the AI accelerator IC (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraphs 35 and 38)(The broadest reasonable interpretation of a chiplet device is processing logic that is configured to perform parallel operations. Volos disclosed multiple compute nodes (i.e. destination devices) to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. The set of compute nodes reads upon a chiplet device. Additionally, official notice is given that compute nodes can implement multiple processing blocks for the advantage of parallel execution. Thus, it would have been obvious to implement the compute nodes of Volos within Nield that each perform parallel operations.);
a task dispatcher module coupled to each of the plurality of cells in the task queue module and configured to asynchronously dispatch the work unit stored in each of the plurality of cells to one of the plurality of destination devices in a parallel pipeline process using a bus device coupled to the task queue module such that each cell is configured to communicate through the bus device to one of the plurality of destination devices (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 4 elements 106 and 410, paragraphs 35-36, 38, and 50)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. Nield disclosed a task scheduling engine (i.e. task dispatcher module) that asynchronously schedules ready tasks when processing blocks become available. Official notice is given that buses can be used to transfer data between logic elements for the advantage of moving data around processing elements for further processing. Thus, it would have been obvious to implement buses between the task scheduling engine, task queue, and processing blocks so that ready tasks can be sent to processing blocks for execution.).
The advantage of using tasksets is that larger tasks can be broken up into smaller tasks for parallel execution. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement creating the tasksets of Volos in Nield for the above advantage.
Nield and Volos failed to teach a resource monitor module coupled to each of the plurality of cells in the task queue module and configured to monitor a state of each of the plurality of destination devices.
However, Tanaka combined with Nield and Volos disclosed a resource monitor module coupled to each of the plurality of cells in the task queue module and configured to monitor a state of each of the plurality of destination devices (Tanaka: Figures 1, 6, and 8 elements 202-204 and 207, paragraphs 46 and 52-53)(Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraph 35)(Tanaka disclosed a load monitor (i.e. resource monitor) that saves a load condition of the logical processors. The combination allows for implementing a load monitor within Nield that monitors and saves load conditions of processing blocks (i.e. destination devices).).
The advantage of monitoring processor loads is that tasks can be better allocated to processors with available processing capacity. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the load monitoring of Tanaka within Nield for the above advantage.
As per claim 2:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the hierarchy of queues includes one or more concurrent queues, each of the concurrent queues having at least a portion of the plurality of work units of the task group, and wherein the task queue module is configured to store each such work unit in one of the plurality of cells (Volos: Figures 1-2 and 4 elements 104-1-n and 104w-1-2, paragraphs 16-17, 31, and 45)(Nield: Figures 1 and 4 elements 106 and 410, paragraphs 35-36, 38, and 50)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. The combination allows for Nield to receive tasks that are part of a taskset and set dependencies between tasks. Tasks t1-2 to t1-5 are placed within entries of the task queue of Nield.).
As per claim 3:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the hierarchy of queues includes one or more serial queues, each of the serial queues having at least a portion of the plurality of work units of the task group, and wherein the task queue module is configured to store each such work unit in one of the plurality of cells and to store one or more task queue barriers configured to cause the task dispatcher module to dispatch the portion of the plurality of work units stored in the plurality of cells in a serial process (Volos: Figures 1-2 and 4 elements 104-1-n and 104w-1-2, paragraphs 16-17, 31, and 45)(Nield: Figures 1 and 4 elements 106 and 410, paragraphs 35-36, 38, and 50)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. The combination allows for Nield to receive tasks that are part of a taskset and set dependencies between tasks. Tasks t1-1 to t3-1 are placed within entries of the task queue of Nield. Serial execution of tasks t1-6, t2-1, and t2-2 occurs based on dependencies.).
As per claim 4:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the resource monitor module is configured to monitor the state of each of the plurality of destination devices by inferentially checking the status of each of the plurality of cells (Tanaka: Figures 1, 6, and 8 elements 202-204 and 207, paragraphs 46 and 52-53)(Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraph 35)(Tanaka disclosed a load monitor (i.e. resource monitor) that saves a load condition of the logical processors. The combination allows for implementing a load monitor within Nield that monitors and saves load conditions of processing blocks (i.e. destination devices). The real-time state of the processing blocks can be inferred by checking the saved load conditions, which aren’t real-time conditions.).
As per claim 5:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the resource monitor module is configured to monitor the state of each of the plurality of destination devices by polling each destination device using the bus device (Tanaka: Figures 1, 6, and 8 elements 202-204 and 207, paragraphs 46 and 52-53)(Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraph 35)(Tanaka disclosed a LPAR controller (i.e. resource monitor) that examines a load condition of the logical processors. Official notice is given that checking can be performed by polling for the advantage of knowing the load condition at set periods of time. Thus, it would have been obvious to one of ordinary skill in the art to implement polling as the method of checking by the LPAR controller. The combination allows for implementing a load monitor within Nield that monitors and saves load conditions of processing blocks (i.e. destination devices).).
As per claim 6:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the task queue module is coupled to a CPU device, the CPU device being coupled to each of the plurality of cells in the task queue module and configured to transfer each of the plurality of work units of the one or more task groups into one of the plurality of cells in the task queue module according to the hierarchy of queues (Volos: Figure 4, paragraphs 29 and 35-36)(Nield: Figures 1 and 3 elements 108-110, 120, and 302-304, paragraphs 35-36, 39-40, and 44-45)(Nield discloses receiving tasks, but doesn’t detail where the tasks originate from. Official notice is given that host CPUs can be used to output tasks to coprocessors for the advantage of accelerated processing. Thus, it would have been obvious to one of ordinary skill in the art to implement a host CPU within Nield. The combination allows for Nield to receive tasks from the host CPU that are part of a taskset and set dependencies between tasks. The received tasks that are part of tasksets are stored within the task queue storage elements. Setting dependencies between tasks allows for a hierarchy of stored tasks within the task queue.); and
wherein the CPU device is configured to determine the hierarchy of queues for each of the one or more task groups (Volos: Figure 4, paragraphs 29 and 35-36)(Nield: Figures 1 and 3 elements 108-110, 120, and 302-304, paragraphs 35-36, 39-40, and 44-45)(The combination allows for Nield to receive tasks from the host CPU that are part of a taskset and set dependencies between tasks. The receives tasks that are part of tasksets are stored within the task queue storage elements. Setting dependencies between tasks allows for a hierarchy of stored tasks within the task queue. In view of the above official notice, the task dependencies are determined by the host CPU.).
As per claim 7:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the completion handler module is coupled to a CPU device, the completion handler module being configured to send the completion signal to the CPU device (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 5A-B elements 104, 108, and 502, paragraphs 35, 38, and 55-56)(The logic that generates an indication that a task has been completed reads upon the completion handler. Official notice is given that host CPUs can be used to output tasks to coprocessors and receive updates from the coprocessors for the advantage of accelerated processing. Thus, it would have been obvious to one of ordinary skill in the art to implement a host CPU within Nield. The host CPU receives updates when the tasks are finished processing.).
As per claim 8:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the completion condition includes a completion of a work unit stored in one of the plurality of cells in the task queue module by one of the plurality of destination devices, or a completion of a task group stored in the plurality of cells in the task queue module by the plurality of destination devices (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 5A-B elements 104, 108, and 502, paragraphs 35, 38, and 55-56)(The logic that generates an indication that a task has been completed reads upon the completion handler. Nield disclosed a single processing block for executing scheduled tasks. Volos disclosed multiple compute nodes to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. As such, the completion indication can be for a task of a taskset or the last task of a taskset stored in the task queue.).
As per claim 9:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the task dispatcher module is configured to asynchronously dispatch the unit of work stored in each of the plurality of cells to one of the plurality of destination devices based on the state of the destination device (Tanaka: Figures 1, 6, and 8 elements 202-204 and 207, paragraphs 46 and 52-53)(Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 4 elements 106 and 410, paragraphs 35-36, 38, and 50)(The combination allows for implementing a load monitor within Nield that monitors and saves load conditions of processing blocks (i.e. destination devices). The combination implements a plurality of processing blocks in Nield for parallel execution of multiple tasks. Nield disclosed a task scheduling engine (i.e. task dispatcher module) that asynchronously schedules ready tasks when processing blocks become available based on the saved load conditions.).
As per claim 10:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the completion handler module is configured to determine the completion of each of the plurality of work units of each task group (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 5A-B elements 104, 108, and 502, paragraphs 35, 38, and 55-56)(The logic that generates an indication that a task has been completed reads upon the completion handler. Nield disclosed a single processing block for executing scheduled tasks. Volos disclosed multiple compute nodes to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. As such, the completion indication can be for a task of a taskset or the last task of a taskset stored in the task queue.) and to track a completion count of the plurality of work units to determine the completion of each task group (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1, 4, and 5A-B elements 104, 108, 410, and 502, paragraphs 35, 38, 40, and 55-56)(Nield disclosed a dependency counter that decrements as tasks are completed. Volos disclosed multiple compute nodes to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. As such, tasks t2-1 can store 4 dependencies and decrement to zero as tasks t1-2, t1-3, t1-5, and t1-6 complete. This countdown indicates when taskset 1 has completed.).
As per claim 11:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the task dispatcher module is configured to determine when a target task group is ready to be dispatched and to update the task queue module when a target work unit is dispatched (Volos: Figures 1-2 and 3B elements 104-1-n and 104w-1-2, paragraphs 16-17, 31, and 37-41)(Nield: Figures 1 and 4 elements 106 and 410, paragraphs 35-36, 38, and 50)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. Nield disclosed a task scheduling engine (i.e. task dispatcher module) that asynchronously schedules ready tasks when processing blocks become available. The combination allows for the scheduler and task queue of Nield to track the state of the task (e.g. change state from pending to running on dispatch).).
As per claim 12:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 wherein the resource monitor module is configured to communicate with the task dispatcher module when a target destination device is available, and wherein the task dispatcher module is configured to communicate with the resource monitor module to update a status of the target destination device (Tanaka: Figures 1, 6, and 8 elements 202-204 and 207, paragraphs 46 and 52-53)(Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraph 35)(Tanaka disclosed a load monitor (i.e. resource monitor) that saves a load condition of the logical processors. The combination allows for implementing a load monitor within Nield that monitors and saves load conditions of processing blocks (i.e. destination devices). The load monitor and scheduler each communicate with each other regarding load conditions and scheduling.).
As per claim 13:
Nield, Volos, and Tanaka disclosed the apparatus of claim 1 further comprising a clocking device coupled to a CPU device, the CPU device being configured to write to each of the cells with the work unit at a rate of once every ten clock cycles to once every clock cycle (Volos: Figure 4, paragraphs 29 and 35-36)(Nield: Figures 1 and 3 elements 108-110, 120, and 302-304, paragraphs 35-36, 39-40, and 44-45)(Nield discloses receiving tasks, but doesn’t detail where the tasks originate from. Official notice is given that host CPUs can be used to output tasks to coprocessors using processor clocks for the advantage of accelerated processing and synchronizing processor functions. Thus, it would have been obvious to one of ordinary skill in the art to implement a host CPU within Nield. The combination allows for Nield to receive tasks from the host CPU that are part of a taskset based on processor clocks. Clocking outputs from a host CPU to the task queue configures the scheduler to receive and write tasks to the task queue between one and ten clock cycles.), and configured to operate the plurality of destination devices at a pre-defined efficiency of 80% to 90% (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figures 1 and 5A-B elements 104, 108, and 502, paragraphs 35, 38, and 55-56)(Nield disclosed a single processing block for executing scheduled tasks. Volos disclosed multiple compute nodes to execute multiple tasks in parallel. The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. The processing blocks are configured to operate between 80-90% efficiency when the task queue is filled to a degree that allows for processing to occur 80-90% of the time. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
As per claim 14:
Claim 14 essentially recites the same limitations of claim 1. Therefore, claim 14 is rejected for the same reasons as claim 1.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claims 2 or 3. Therefore, claim 15 is rejected for the same reason(s) as claims 2 or 3.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claims 6 and 13. Therefore, claim 16 is rejected for the same reason(s) as claims 6 and 13.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claims 7-8 and 10. Therefore, claim 17 is rejected for the same reason(s) as claims 7-8 and 10.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claims 4-5 and 12. Therefore, claim 18 is rejected for the same reason(s) as claims 4-5 and 12.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 11. Therefore, claim 19 is rejected for the same reason(s) as claim 11.
As per claim 20:
Claim 20 essentially recites the same limitations of claim 1. Claim 20 additionally recites the following limitations:
a CPU coupled to the plurality of destination devices via a crossbar device (Volos: Figures 1-2 elements 104-1-n and 104w-1-2, paragraphs 16-17 and 31)(Nield: Figure 1 elements 104 and 108, paragraphs 35 and 38)(The combination allows for a plurality of processing blocks in Nield for parallel execution of multiple tasks. Official notice is given that processing systems can include CPUs for the advantage of performing general processing tasks. Thus, it would have been obvious to one of ordinary skill in the art to implement a CPU in the combination. Additionally, official notice is given that crossbars can be used to connect processing elements together for the advantage of sharing and communicating data. Thus, it would have been obvious to one of ordinary skill in the art to implement a crossbar to connect the CPU to the compute nodes.).
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Sevigny (U.S. 2017/0132037), taught a job scheduler.
Lu et al. (U.S. 2016/0070603), taught a task queue.
Lin et al. (U.S. 2019/0146705), taught a 2D process queue.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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