DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Viswanathan Pillai (U.S. Patent Application Publication No. 2023/0068811), hereinafter “Pillai”.
Regarding claim 1, Pillai discloses an apparatus for fault detection in a dual core lockstep microcontroller (fig. 2), the apparatus comprising:
a first central processing circuitry to execute a set of instructions (primary hardware 202, [0038, 0039], fig. 2);
one or more second central processing circuitries operating in parallel with the first central processing circuitry to execute the set of instructions (secondary hardware 204, [0038, 0039], fig. 2);
a first comparator to compare an output from the first central processing circuitry with an output from the one or more second central processing circuitries (first comparator 214, [0038], fig. 2, 4A);
one or more second comparators to compare the output from the first central processing circuitry with the output from the one or more second central processing circuitries (second comparator 216, [0038], fig. 2, 4B); and
at least one logic gate to receive output signals from the first comparator and the one or more second comparators to trigger a fault signal based on the received output signals ([0038, 0129, 0130, 0138, 0139], fig. 2, 4A, 4B).
Regarding claim 5, Pillai discloses wherein the at least one logic gate is an OR gate ([0059, 0061, 0079], fig. 3, 4A, 4B).
Regarding claim(s) 7 and 11, claim(s) 7 and 11 recite(s) substantially similar limitations to claim(s) 1 and 5 and is(are) therefore rejected using the same art and rationale set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 6, 8, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillai, as applied to claim 1 above, in view of Takahashi (U.S. Patent Application Publication No. 2010/0308867).
Regarding claim 2, Pillai discloses the system as set forth above.
Pillai does not expressly disclose a reset controller operatively coupled to receive the fault signal from the at least one logic gate;
wherein the reset controller is to transmit a machine check reset signal responsive to the fault signal received from the at least one logic gate to trigger a reset of the apparatus.
Takahashi teaches that it was known in the art to have a reset controller operatively coupled to receive the fault signal from the at least one logic gate (reset control circuit 104, [0037-0039], fig. 1);
wherein the reset controller is to transmit a machine check reset signal responsive to the fault signal received from the at least one logic gate to trigger a reset of the apparatus (reset control circuit 104, [0037-0039], fig. 1).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai by including the reset controller as taught by Takahashi.
One of ordinary skill would have been motivated to make the combination, in order to predict and prevent abnormalities ([0008], Takahashi).
Regarding claim 6, Takahashi discloses wherein the first central processing circuitry comprises a first interrupt controller to receive an interrupt signal ([0037]);
wherein the one or more second central processing circuitries comprise one or more second interrupt controllers to receive the interrupt signal ([0037]); and
wherein the interrupt signal is received by the first interrupt controller and the one or more second interrupt controllers in response to the machine check reset signal to indicate that the fault signal has been triggered by the at least one logic gate (the reset signal 115 from the reset control circuit 104 may be supplied to the first CPU 101 and the second CPU 102 as a reset interrupt signal. In this case, when the reset signal 115 from the reset control circuit 104 is activated, each of the first CPU 101 and the second CPU 102 executes a halt instruction (Halt) or executes a shutdown process, as an interrupt process for activation of the reset signal 115, for example. When the reset signal 115 from the reset control circuit 104 is activated, the other circuits 106 execute a reset operation such as an operation stop, [0037]).
Regarding claim(s) 8 and 12, claim(s) 8 and 12 recite(s) substantially similar limitations to claim(s) 2 and 6 and is(are) therefore rejected using the same art and rationale set forth above.
Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillai, as applied to claim 1 above, in view of Lassen (U.S. Patent Application Publication No. 2021/0159688).
Regarding claim 3, Pillai discloses the system as set forth above.
Pillai does not expressly disclose an error controller operatively coupled to receive the fault signal from the at least one logic gate;
wherein the error controller is to transmit an input/output (IO) float signal responsive to the fault signal received from the at least one logic gate to trigger an electrically floating state of one or more IO pins of the apparatus.
Lassen teaches that it was known in the art to have an error controller operatively coupled to receive the fault signal from the at least one logic gate ([0021]);
wherein the error controller is to transmit an input/output (IO) float signal responsive to the fault signal received from the at least one logic gate to trigger an electrically floating state of one or more IO pins of the apparatus (The intended behavior of a typical watchdog circuit, if a critical fault occurs, is to reset the microcontroller (e.g., via the reset controller, without limitation), which also floats the I/O pins (e.g., all the I/O pins, without limitation). Floating the I/O pins is considered a safe state in a safety critical system, since this is a normal situation until the microcontroller has started up. While watchdog circuits and windowed watchdog circuits trigger reset controllers to initiate system resets (e.g., internally in the processing circuit, without limitation), malfunctions in the reset controllers themselves may prevent the triggering of a safe state, and may even prevent system resets. By way of non-limiting example, a fault in the reset controller may prevent placement of the microcontroller in a safe state even if the watchdog circuit detects a fault, [0021]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai by including the error controller as taught by Lassen.
One of ordinary skill would have been motivated to make the combination, in order to avoid unsafe operation of external devices that interact with the processing circuit ([0003], Lassen).
Regarding claim(s) 9, claim(s) 9 recite(s) substantially similar limitations to claim(s) 3 and is(are) therefore rejected using the same art and rationale set forth above.
Claim(s) 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillai in view of Unesaki (U.S. Patent Application Publication No. 2015/0074473).
Regarding claim 4, Pillai discloses the system as set forth above.
Pillai does not expressly disclose an error injection circuit operatively coupled to at least one of the one or more second comparators to selectively inject errors to modify or replace one or more of the output signals of the one or more second comparators to test the fault signal.
Unesaki teaches that it was known in the art to have an error injection circuit operatively coupled to at least one of the one or more second comparators to selectively inject errors to modify or replace one or more of the output signals of the one or more second comparators to test the fault signal ([0055-0057], fig. 7).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai by including the error injection as taught by Unesaki.
One of ordinary skill would have been motivated to make the combination, in order to check the operation of a test target circuit at the time of occurrence of an error by injecting a pseudo-error to the test target circuit ([0003], Unesaki).
Regarding claim(s) 10, claim(s) 10 recite(s) substantially similar limitations to claim(s) 4 and is(are) therefore rejected using the same art and rationale set forth above.
Claim(s) 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillai in view of Takahashi and Lassen.
Regarding claim 13, Pillai discloses an apparatus for fault detection in a dual core lockstep microcontroller (fig. 2), the apparatus comprising:
a first central processing circuitry to execute a set of instructions (primary hardware 202, [0038, 0039], fig. 2);
one or more second central processing circuitries operating in parallel with the first central processing circuitry to execute the set of instructions (secondary hardware 204, [0038, 0039], fig. 2);
a first comparator to compare an output from the first central processing circuitry with an output from the one or more second central processing circuitries (first comparator 214, [0038], fig. 2, 4A);
one or more second comparators to compare the output from the first central processing circuitry with the output from the one or more second central processing circuitries (second comparator 216, [0038], fig. 2, 4B); and
at least one logic gate to receive output signals from the first comparator and the one or more second comparators to trigger a fault signal based on the received output signals ([0038, 0129, 0130, 0138, 0139], fig. 2, 4A, 4B).
Pillai does not expressly disclose a reset controller operatively coupled to receive the fault signal from the at least one logic gate, and to transmit a machine check reset signal responsive to the fault signal received from the at least one logic gate to trigger a reset of the apparatus; and
an error controller operatively coupled to receive the fault signal from the at least one logic gate, and to transmit an input/output (IO) float signal responsive to the fault signal received from the at least one logic gate to trigger an electrically floating state of one or more IO pins of the apparatus.
Takahashi teaches that it was known in the art to have a reset controller operatively coupled to receive the fault signal from the at least one logic gate, and to transmit a machine check reset signal responsive to the fault signal received from the at least one logic gate to trigger a reset of the apparatus (reset control circuit 104, [0037-0039], fig. 1).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai by including the reset controller as taught by Takahashi.
One of ordinary skill would have been motivated to make the combination, in order to predict and prevent abnormalities ([0008], Takahashi).
Lassen teaches that it was known in the art to have an error controller operatively coupled to receive the fault signal from the at least one logic gate, and to transmit an input/output (IO) float signal responsive to the fault signal received from the at least one logic gate to trigger an electrically floating state of one or more IO pins of the apparatus (The intended behavior of a typical watchdog circuit, if a critical fault occurs, is to reset the microcontroller (e.g., via the reset controller, without limitation), which also floats the I/O pins (e.g., all the I/O pins, without limitation). Floating the I/O pins is considered a safe state in a safety critical system, since this is a normal situation until the microcontroller has started up. While watchdog circuits and windowed watchdog circuits trigger reset controllers to initiate system resets (e.g., internally in the processing circuit, without limitation), malfunctions in the reset controllers themselves may prevent the triggering of a safe state, and may even prevent system resets. By way of non-limiting example, a fault in the reset controller may prevent placement of the microcontroller in a safe state even if the watchdog circuit detects a fault, [0021]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai by including the error controller as taught by Lassen.
One of ordinary skill would have been motivated to make the combination, in order to avoid unsafe operation of external devices that interact with the processing circuit ([0003], Lassen).
Regarding claim 15, Pillai discloses wherein the at least one logic gate is an OR gate ([0059, 0061, 0079], fig. 3, 4A, 4B).
Regarding claim 16, Takahashi discloses wherein the first central processing circuitry comprises a first interrupt controller to receive an interrupt signal ([0037]);
wherein the one or more second central processing circuitries comprise one or more second interrupt controllers to receive the interrupt signal ([0037]); and
wherein the interrupt signal is received by the first interrupt controller and the one or more second interrupt controllers in response to the machine check reset signal to indicate that the fault signal has been triggered by the at least one logic gate (the reset signal 115 from the reset control circuit 104 may be supplied to the first CPU 101 and the second CPU 102 as a reset interrupt signal. In this case, when the reset signal 115 from the reset control circuit 104 is activated, each of the first CPU 101 and the second CPU 102 executes a halt instruction (Halt) or executes a shutdown process, as an interrupt process for activation of the reset signal 115, for example. When the reset signal 115 from the reset control circuit 104 is activated, the other circuits 106 execute a reset operation such as an operation stop, [0037]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillai in view of Takahashi and Lessen, as applied to claim 13 above, and further in view of Unesaki.
Regarding claim 14, Pillai as modified by Takahashi and Lessen discloses the system as set forth above.
Pillai does not expressly disclose an error injection circuit operatively coupled to at least one of the one or more second comparators to selectively inject errors to modify or replace one or more of the output signals of the one or more second comparators to test the fault signal.
Unesaki teaches that it was known in the art to have an error injection circuit operatively coupled to at least one of the one or more second comparators to selectively inject errors to modify or replace one or more of the output signals of the one or more second comparators to test the fault signal ([0055-0057], fig. 7).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the system of Pillai as modified by Takahashi and Lessen by including the error injection as taught by Unesaki.
One of ordinary skill would have been motivated to make the combination, in order to check the operation of a test target circuit at the time of occurrence of an error by injecting a pseudo-error to the test target circuit ([0003], Unesaki).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA P LOTTICH whose telephone number is (571)270-3738. The examiner can normally be reached Mon - Fri, 9:00am - 5:30pm.
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/JOSHUA P LOTTICH/ Primary Examiner, Art Unit 2113
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