Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12.307.948 and/or in further view of Lui or Zhang as shown in the chart and rejection below. Although the claims at issue are not identical, they are not patentably distinct from each other because they are covering essentially the same subject matter. This is a provisional nonstatutory double patenting rejection.
Instant application (19/187.152) claim
US Patent 12.307.948 claim
1
1 and 14
2
In view of Lui (US 2022.0180784)
3
In view of Lui (US 2022.0180784)
4
2
5
1
6
3
7
4
8
1
9
5
10
6
11
7
12
1
13
8
14
9
15
10
16
1
17
11
18
12
19
14
20
16 in further view of ‘948 disclosure
Regarding claim 2, the rejection of claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 14 of U.S. Patent No. 12.307.948 is incorporated herein. Claim 2 is not explicit as to, but Lui disclose:
a first end of the first electrostatic discharge circuit is coupled to a third frame start signal line, and a first end of the second electrostatic discharge circuit is coupled to a fourth frame start signal line (see Fig. 6, 7a; first electrostatic discharge circuit ESD1 coupled to third frame start line Data1; second ESD2 coupled to fourth frame start line Data2).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention to combine the known techniques of Lui to that of the ‘948 patent to predictably provide electrostatic discharge circuits to frame start lines in order reduce risk of damage to the display through the ESD ([0054]).
Regarding claim 3, the rejection of claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 14 of U.S. Patent No. 12.307.948 is incorporated herein. Claim 2 is not explicit as to, but Lui disclose:
the first electrostatic discharge circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, and the first electrostatic discharge circuit is coupled to the first gate driving circuit; and the second electrostatic discharge circuit comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, and the second electrostatic discharge circuit is coupled to the second gate driving circuit (see Fig. 6, 7a; ESD1 has 13th TFT T12, 14th TFT T11, 15th TFT T10, 16th TFT T9; ESD2 has 12th TFT T12, 11th TFT T11, 10th TFT T10, 9th TFT T9).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention to combine the known techniques of Lui to that of the ‘948 patent to predictably provide electrostatic discharge circuits in order reduce risk of damage to the display through the ESD ([0054]).
Regarding claim 20, claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12.307.948 in view of the ‘948 disclosure. While claim 16 discloses: making the plurality of first gate driving circuits and the plurality of second gate driving circuits, the first gate driving signal output by the first gate driving circuit and the second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line Claim 16 is not explicit as to, but the ‘948 disclosure in the [abstract] and col. 3, ln. 65 – col. 4 line 9 together describe a method of manufacturing a display substrate, wherein the display substrate discloses first and second electrostatic discharge circuits sharing at least one signal line. Therefore, such additional method of manufacture would be obvious to one of ordinary skill in the art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2022.0301497) in view of Lui (US 2022.0180784).
Regarding claim 1, Zhang disclose:
A display substrate, comprising: a plurality of first gate driving circuits and a plurality of second gate driving circuits, wherein a first gate driving signal output by the first gate driving circuit and a second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line (see Fig. 1, 5-7, 14; first gate circuit 2/20; second gate circuit 3/30 with different timing (out1 vs out2), sharing signal line VGL1).
Zhang is not explicit as to, but Lui disclose:
wherein the display substrate further comprises: a first electrostatic discharge circuit, the first electrostatic discharge circuit being coupled to the first gate driving circuit; a second electrostatic discharge circuit, the second electrostatic discharge circuit being coupled to the second gate driving circuit (see Fig. 6, 7a; [0071]; first ESD circuit ESD1 coupled to GOA1; second EST circuit ESD2 coupled to GOA2)
wherein the first electrostatic discharge circuit and the second electrostatic discharge circuit share a first level signal line and a second level signal line (see Fig. 6, 7a; [0071where ESD1 and ESD2 share a first and second level signal lines VGH an VGL)
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention to combine the known techniques of Lui to that of Zhang to predictably provide electrostatic discharge circuits in order reduce risk of damage to the display through the ESD ([0054]).
Regarding claim 2, the rejection of claim 1 is incorporated herein. Lui further disclose:
a first end of the first electrostatic discharge circuit is coupled to a third frame start signal line, and a first end of the second electrostatic discharge circuit is coupled to a fourth frame start signal line (see Fig. 6, 7a; first electrostatic discharge circuit ESD1 coupled to third frame start line Data1; second ESD2 coupled to fourth frame start line Data2).
Regarding claim 3, the rejection of claim 1 is incorporated herein. Lui further disclose:
the first electrostatic discharge circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, and the first electrostatic discharge circuit is coupled to the first gate driving circuit; and the second electrostatic discharge circuit comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, and the second electrostatic discharge circuit is coupled to the second gate driving circuit (see Fig. 6, 7a; ESD1 has 13th TFT T12, 14th TFT T11, 15th TFT T10, 16th TFT T9; ESD2 has 12th TFT T12, 11th TFT T11, 10th TFT T10, 9th TFT T9).
Regarding claim 4, the rejection of claim 1 is incorporated herein. Zhang further disclose:
the display substrate comprises a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits and the plurality of second gate driving circuits are all arranged in the peripheral area; at least part of the first gate driving circuits and at least part of the second gate driving circuits are symmetrically arranged in a peripheral area close to a same side of the display area (see Fig. 1, 5)
Regarding claim 5, the rejection of claim 4 is incorporated herein. Zhang further disclose:
the first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal having a first level (see [0061]; share VGL1 with constant signals)
Regarding claim 6, the rejection of claim 5 is incorporated herein. Zhang further disclose:
at least part of an orthographic projection of the first level signal line on a base substrate of the display substrate is located between an orthographic projection of the first gate driving circuit on the base substrate and an orthographic projection of the second gate driving circuit on the base substrate (see Fig. 14)
Regarding claim 7, the rejection of claim 6 is incorporated herein. Zhang further disclose:
the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the first gate driving circuit on the base substrate; and/or, the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate (see Fig. 1, 5-7, and 14; where VGL1 partly overlaps first gate circuit 2/20 and second gate circuit 3/30)
Regarding claim 8, the rejection of claim 5 is incorporated herein. Zhang further disclose:
the first gate driving circuit and the second gate driving circuit share a first clock signal line and/or a second clock signal line, a phase of a first clock signal transmitted by the first clock signal line is opposite to a phase of a second clock signal transmitted by the second clock signal line (see Fig. 6-7; share clock signal CL and XCL in opposite phase)
Regarding claim 9, the rejection of claim 8 is incorporated herein. Zhang further disclose:
at least part of the first gate driving circuits and at least part of the second gate driving circuits are arranged symmetrically with respect to a first symmetry axis; the first symmetry axis at least partially overlaps the first clock signal line, or the first symmetry axis at least partially overlaps the second clock signal line, or the first symmetry axis at least partially overlaps the first level signal line (see Fig. 5, 14; where symmetry axis (vertical line between 2/20 and 3/30) overlaps VGL)
Regarding claim 10, the rejection of claim 8 is incorporated herein. Zhang further disclose:
the orthographic projection of the first level signal line on the base substrate is located between an orthographic projection of the first clock signal line on the base substrate and an orthographic projection of the second clock signal line on the base substrate (see Fig. 14; VGL between CK and XCK)
Regarding claim 11, the rejection of claim 8 is incorporated herein. While Zhang discloses various arrangements of the drive circuits, its not shown that the clock connections are overlapped, except in Fig. 15. Thus, in light of the disclosure of Fig. 15, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention to combine the known techniques of Fig. 15 of Zhang to predictably provide CK/XCK connections to overlap the first and second gate driving circuits in order to connect to the transistors within. Therefore, Zhang at Fig. 15 disclose:
the orthographic projection of the first clock signal line on the base substrate at least partially overlaps an orthographic projection of one of the first gate driving circuit and the second gate driving circuit on the base substrate; the orthographic projection of the second clock signal line on the base substrate at least partially overlaps an orthographic projection of the other of the first gate driving circuit and the second gate driving circuit on the base substrate (see Fig. 15)
Regarding claim 12, the rejection of claim 8 is incorporated herein. Zhang further disclose:
the first gate driving circuit is coupled to a first frame start signal line, and the second gate driving circuit is coupled to a second frame start signal line (see [0069]; STV1 and STV2)
Regarding claim 13, the rejection of claim 12 is incorporated herein. Zhang further disclose:
the orthographic projection of the first level signal line on the base substrate is located between an orthographic projection of the first frame start signal line on the base substrate and an orthographic projection of the second frame start signal line on the base substrate (see Fig. 14; VGL between STV1 and STV2)
Regarding claim 14, the rejection of claim 12 is incorporated herein. While Zhang discloses various arrangements and connections of the drive circuits it does not describe the overlap of starts signals with the drive circuits, however, in light of the disclosure of Fig. 5, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention to combine disclosure of Zhang at Fig. 5 to predictably provide STV1 and STV2 connections to overlap the first and second gate driving circuits in order to connect to the transistors within (see connection of STV1 and STV2 to gate drive circuits 30 and 20, respectively . Therefore, Zhang at Fig. 5 disclose:
the orthographic projection of the first frame start signal line on the base substrate at least partially overlaps the orthographic projection of the first gate driving circuit on the base substrate; the orthographic projection of the second frame start signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate (see Fig. 5)
Regarding claim 15, the rejection of claim 12 is incorporated herein. While Zhang discloses various arrangements and connections of the drive circuits, claim 13 subject matter is not claimed or described to have the “the orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate are located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate” as essential, thus would be an obvious design choice. Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate are located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate of Zhang, since it has been held that rearranging parts of an invention involved only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Regarding claim 17, the rejection of claim 1 is incorporated herein. Zhang further disclose:
a width-to-length ratio of a channel of an output transistor included in the first gate driving circuit is equal to or greater than a width-to-length ratio of a channel of an output transistor included in the second gate driving circuit (see Fig. 14; where output transistors of first and second gave driving circuits are the same)
Regarding claim 18, the rejection of claim 1 is incorporated herein. Zhang further disclose:
the display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light emitting elements, a plurality of data lines, a plurality of second initialization signal lines and a plurality of third initialization signal lines, the first sub-pixel driving circuit includes a first driving transistor, a first data writing-in transistor, a first compensation transistor, a second reset transistor and a third reset transistor; a gate electrode of the first data writing-in transistor is coupled to an output terminal of a corresponding first gate driving circuit, and a first electrode of the first data writing-in transistor is coupled to a corresponding data line, and a second electrode of the first data writing- in transistor is coupled to a first electrode of the first driving transistor; a gate electrode of the first compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, and a first electrode of the first compensation transistor is coupled to a second electrode of the first driving transistor, a second electrode of the first compensation transistor is coupled to a gate electrode of the first driving transistor; a gate electrode of the second reset transistor is coupled to an output terminal of a corresponding second gate driving circuit, and a first electrode of the second reset transistor is coupled to a corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to a corresponding light emitting element; a gate electrode of the third reset transistor is coupled to the output terminal of the corresponding second gate driving circuit, and a first electrode of the third reset transistor is coupled to a corresponding third initialization signal line, and a second electrode of the third reset transistor is coupled to the first electrode of the first driving transistor (see Fig. 1-2; display first subpanel driving circuit 12; light emitting element 11; data lines Vdata; second in initialization line Vref2; 3rd initialization line Vref2; drive TFT M0; data TFT M6 compensation TFT M1; second reset M7; third reset M7; gate of M6 output terminal S2, data line Vdata, second electrode coupled to M0; gate of M1 connected to output terminal Sn, first electrode coupled to Mo, second electrode coupled gate of MO; gate of second reset M7 coupled to output terminal S2, first electrode to second initialization line Vref2, second electrode coupled to PVEE; gate of third reset M7 coupled to output terminal S2; first electrode connected to third initialization Vref2, second electrode connected to first electrode of MO via M4)
Regarding claim 19, the rejection of claim 1 is incorporated herein. Lui further disclose:
the first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged symmetrically (see Fig. 7a where ESD1 and ESD2 same arrangement, thus symmetrically arranged).
Regarding claim 20, the rejection of claim 1 is incorporated herein. Zhang further disclose:
making the plurality of first gate driving circuits and the plurality of second gate driving circuits, the first gate driving signal output by the first gate driving circuit and the second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line (see Fig. 1, 5-7, 14; [0058] method of manufacturing the display).
Furthermore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicants invention to also provide a method of manufacture for making a first electrostatic discharge circuit and a second electrostatic discharge circuit; and wherein the first electrostatic discharge circuit being coupled to the first gate driving circuit, the second electrostatic discharge circuit being coupled to the second gate driving circuit, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share a first level signal line and a second level signal line, of Lui in light of [0058] of Zhang describing a method of manufacturing a display.
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the double patenting rejection is overcome
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH BUKOWSKI whose telephone number is (571)270-7913. The examiner can normally be reached Monday - Friday // 0730-1530.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571.272.7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/kenneth bukowski/Primary Examiner, Art Unit 2621