DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 16 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,323,134. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant
application is broader than claim 1 of U.S. Patent No. 12,323,134 by omitting other
features recited in claim 1 such as “a supplemental electrode and wherein the insulated gate bipolar transistor comprises a reverse diode structure electrically connected in parallel to the first transistor cell and the second transistor cell; wherein an operation mode of the reverse diode structure is switchable between an enhanced diode mode and a standard diode mode by a second gate signal applied to the second gate; and wherein a forward conductivity of the reverse diode structure in the enhanced diode mode is higher than a second forward conductivity of the reverse diode structure in the standard diode mode”
Claims 18-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4-5 of U.S. Patent No. 12,323,134. (see table below)
Instant application 19/187,273
US Patent 12,323,134
16. A semiconductor switching module, comprising: an insulated gate bipolar transistor comprising: a first transistor cell comprising a first gate and a first source; and a second transistor cell comprising a second gate and a second source; and a unipolar switching device based on a wide bandgap material and comprising a third gate and a third source, wherein the third gate is electrically connected with the second gate; wherein the third gate and the second gate are disconnected from the first gate; and wherein the first source, the second source and the third source are electrically connected with each other.
20. The semiconductor switching module according to claim 16, wherein: the insulated gate bipolar transistor comprises a reverse diode structure electrically connected in parallel to the first transistor cell and the second transistor cell; an operation mode of the reverse diode structure is switchable between an enhanced diode mode and a standard diode mode by a second gate signal applied to the second gate; and a forward conductivity of the reverse diode structure in the enhanced diode mode is higher than a second forward conductivity of the reverse diode structure in the standard diode mode.
1. A semiconductor switching module, comprising: an insulated gate bipolar transistor comprising: a first transistor cell comprising a first gate and a first source; and a second transistor cell comprising a second gate and a second source comprising a supplemental electrode; and a unipolar switching device based on a wide bandgap material and comprising a third gate and a third source, wherein the third gate is electrically connected with the second gate; wherein the third gate and the second gate are disconnected from the first gate; wherein the first source, the supplemental electrode and the third source are electrically connected with each other; wherein the insulated gate bipolar transistor comprises a reverse diode structure electrically connected in parallel to the first transistor cell and the second transistor cell; wherein an operation mode of the reverse diode structure is switchable between an enhanced diode mode and a standard diode mode by a second gate signal applied to the second gate; and wherein a forward conductivity of the reverse diode structure in the enhanced diode mode is higher than a second forward conductivity of the reverse diode structure in the standard diode mode.
18. The semiconductor switching module according to claim 16, comprising: a short-circuit protection unit configured to omit turning on the unipolar switching device and the second transistor cell if a short-circuit condition is detected.
4. The semiconductor switching module according to claim 1, comprising: a short-circuit protection unit configured to omit turning on the unipolar switching device and the second transistor cell if a short-circuit condition is detected.
19. The semiconductor switching module according to claim 16, comprising: an overcurrent protection unit configured to turn off the unipolar switching device and the second transistor cell when an overcurrent condition is detected.
5. The semiconductor switching module according to claim 1, comprising: an overcurrent protection unit configured to turn off the unipolar switching device and the second transistor cell when an overcurrent condition is detected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-12 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “if a first gate signal and the second gate signal exceed a first threshold voltage” and claim 18 recites “the second transistor cell if a short-circuit condition is detected”. The phrase “if’ renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP 2173.05(d).
Claims 6-12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 2016/0191021 and Zhao hereinafter) in view of Takao et al. (US 20130062626 and Takao hereinafter).
Regarding claim 1, Zhao disclose a method of operating a semiconductor switching module [figs. 2A-3B] comprising an insulated gate bipolar transistor [S2/S3, fig. 2A, par. 0051] and a unipolar switching device [S1, fig. 2A, par. 0051], wherein the insulated gate bipolar transistor comprises: a first transistor cell [S2, fig. 2A] comprising a first gate and a first source; and a second transistor cell [S3, fig. 2A] comprising a second gate and a second source, wherein the unipolar switching device is based on a wide bandgap material [par. 0051] and comprises a third gate and a third source, wherein the third gate and the second gate are disconnected from the first gate, and wherein the first source, the second source and the third source are electrically connected with each other [fig. 2A]. Although, Zhao disclose the wide bandgap switching device [S1] turns on before the IGBTs [S2 and S3] and turns off after the IGBTs [par. 0051 fig. 3B], it does not teach turning on the unipolar switching device [S1] and the second transistor cell [S3] after turning on the first transistor cell [S2]; and turning off the unipolar switching device and the second transistor cell prior to turning off the first transistor cell. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the switching sequence of fig. 3B so that the unipolar switching device [S1] and the second transistor cell [S3] turn on after turning on the first transistor cell [S2]; and turning off the unipolar switching device and the second transistor cell prior to turning off the first transistor cell is a predictable and routine modification of known control techniques of load balancing for power switching applications. Zhao does not explicitly disclose wherein the third gate is electrically connected with the second gate.
However, Takao discloses [fig. 10] a unipolar switching device [1] based on a wide bandgap material [abstract] and an insulated gate bipolar transistor [2] wherein the gate of the unipolar switching device is electrically connected with the gate of the insulated gate bipolar transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Zhao by incorporating the common control gate taught in Takao in order to drive both the Si-IGBT and the wide bandgap semiconductor switching device using a single gate driving circuit [para. 0052- 0055].
Regarding claim 13, Zhao disclose a method of operating a semiconductor switching [figs. 2A-3B] module comprising an insulated gate bipolar transistor [S2/S3, fig. 2A, par. 0051] and a unipolar switching device [S1, fig. 2A, par. 0051], wherein the insulated gate bipolar transistor comprises: a first transistor cell [S2, fig. 2A] comprising a first gate [gate S2] and a first source [source S2]; and a second transistor cell [S3, fig. 2A] comprising a second gate [gate S3] and a second source [source S3], wherein the unipolar switching device is based on a wide bandgap material [par. 0051] and comprises a third gate [gate S3] and a third source [source S3], wherein the third gate and the second gate are disconnected from the first gate, and wherein the first source, the second source and the third source are electrically connected with each other [fig. 2A], the method comprising: detecting, by a light load mode unit, a light load condition [par. 0051]. Although, Zhao disclose in response detecting the light load condition when the wide bandgap switching device (e.g., JFET/MOSFET) is active and determines the overall conducting and switching losses, but the parallel IGBTs remain inactive in response to inactive control signals S2 and S3 [par. 0051], it does not teach turning on at least one of the unipolar switching [S1] device or the second transistor cell [S3] before the first transistor cell [S2] is turned on; and turning off at least one of the unipolar switching device or the second transistor cell prior to turning off the first transistor cell. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the switching sequence of figs. 3A/3B so that the unipolar switching device [S1] and the second transistor cell [S3] turn on after turning on the first transistor cell [S2]; and turning off the unipolar switching device and the second transistor cell prior to turning off the first transistor cell is a predictable and routine modification of known control techniques of load balancing for power switching applications. Zhao does not explicitly disclose wherein the third gate is electrically connected with the second gate.
However, Takao discloses [fig. 10] a unipolar switching device [1] based on a wide bandgap material [abstract] and an insulated gate bipolar transistor [2] wherein the gate of the unipolar switching device is electrically connected with the gate of the insulated gate bipolar transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Zhao by incorporating the common control gate taught in Takao in order to drive both the Si-IGBT and the wide bandgap semiconductor switching device using a single gate driving circuit [para. 0052- 0055].
Regarding claim 14, Zhao disclose all the features with respect to claim 13 as outlined above. Zhao disclose does not explicitly wherein the light load mode comprises a first and a second light load mode, the method further comprising: turning on, in the first light load mode and by the light load mode unit, at least one of the unipolar switching device or the second transistor cell while the first transistor cell remains turned off. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify in the first light load mode the switching sequence of figs. 3A/3B so that at least one of the unipolar switching device or the second transistor cell while the first transistor cell remains turned off is a predictable and routine modification of known control techniques of load balancing for power switching applications.
Regarding claim 15, Zhao disclose all the features with respect to claim 13 as outlined above. Zhao disclose does not explicitly wherein turning on, by the light load mode unit, the unipolar switching device and the second transistor cell before turning on the first transistor cell; and turning off the unipolar switching device and the second transistor cell after turning off the first transistor cell when the light load condition is detected. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify in the first light load mode the switching sequence of figs. 3A/3B so that the unipolar switching device and the second transistor cell before turning on the first transistor cell; and turning off the unipolar switching device and the second transistor cell after turning off the first transistor cell is a predictable and routine modification of known control techniques of load balancing for power switching applications.
Claims 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over RAHIMO et al. (US 2022/0376605 and Rahimo hereinafter) in view of Takao et al.
Regarding claim 16, Rahimo discloses a semiconductor switching module [fig. 5], comprising: an insulated gate bipolar transistor [6/6’] comprising: a first transistor cell [6] comprising a first gate [gate 6] and a first source [source 6]; and a second transistor cell [6’] comprising a second gate [gate 6’] and a second source [source 6’]; and a unipolar switching device [2] based on a wide bandgap material [par. 0037] and comprising a third gate [gate 2] and a third source [source 2]; wherein the third gate and the second gate are disconnected from the first gate; and wherein the first source, the second source and the third source are electrically connected with each other. Takao does not explicitly disclose wherein the third gate is electrically connected with the second gate.
However, Takao discloses [fig. 10] a unipolar switching device [1] based on a wide bandgap material [abstract] and an insulated gate bipolar transistor [2] wherein the gate of the unipolar switching device is electrically connected with the gate of the insulated gate bipolar transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Rahimo by incorporating the common gate as taught in Takao in order to drive both the Si-IGBT and the wide bandgap semiconductor switching device using a single gate driving circuit [par. 0052 -0055].
Regarding claim 18, Rahimo in view of Takao discloses a short-circuit protection unit [9, par. 0063] configured to omit turning on the unipolar switching device and the second transistor cell if a short-circuit condition is detected.
Regarding claim 19, Rahimo in view of Takao discloses comprising: an overcurrent protection unit [9, fig. 5] configured to turn off the unipolar switching device and the second transistor cell when an overcurrent condition is detected [par. 0038].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over RAHIMO et al. in view of Takao et al.
Regarding claim 17, Rahimo in view of Zhao disclose all the features with respect to claim 16 as outlined above. Rahimo in view of Zhao disclose does not explicitly comprising: a unit [9] configured to: turn on the unipolar switching device and the second transistor cell after turning on the first transistor cell; and turn off the unipolar switching device and the second transistor cell prior to turning off the first transistor cell. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the switching sequence so that turn on the unipolar switching device and the second transistor cell after turning on the first transistor cell; and turn off the unipolar switching device and the second transistor cell prior to turning off the first transistor cell is a predictable and routine modification of known control techniques of load balancing for power switching applications.
Allowable Subject Matter
Claim 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5-12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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