CTNF 19/187,451 CTNF 88147 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (lDS) submitted are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over YUN et al. (US 20180294297 A1, hereinafter “ YUN ”), in view of CHOI et al. (US 20220344393 A1, hereinafter “ CHOI ”), and further in view of court Case Law In re Japikse , 86 USPQ 70 . Regarding claim 1 , YUN teaches an image sensor ( Figs. 1&10-13, [0031]: image sensor )comprising: a substrate ( Figs. 10-13, [0071]: Substrate 100 ); a first pixel group disposed on the substrate ( Figs. 10-13, [0071]: LR1, LR2, LR3 and LR4 on the substrate 100 ) to include a first pixel and a second pixel disposed to adjacent to the second pixel in a first direction ( Figs. 10-13, [0071]: LR1 and LR2 in D1 direction ), a third pixel disposed adjacent to the first pixel in a second direction intersecting the first direction, and a fourth pixel disposed adjacent to the second pixel in the second direction ( as illustrated by Figs. 10-13, [0071]: LR3 and LR4 in D2 direction ); a second pixel group ( Figs. 10-13, [0071]: LR5, LR6, LR7 and LR8 on the substrate 100 ) disposed adjacent to the first pixel group in the second direction to include a fifth pixel disposed adjacent to the third pixel in the second direction ( Figs. 10-13, [0071]: LR5 adjacent to LR3 in D2 direction ), and a sixth pixel disposed adjacent to the fourth pixel in the second direction ( Figs. 10-13, [0071]: LR6 adjacent to LR4 in D2 direction ); a first floating diffusion region electrically connected to the first to fourth pixels; a second floating diffusion region electrically connected to the fifth and sixth pixels ( as illustrated by Fig. 10, [0082]: The first floating diffusion region FD1 and the second floating diffusion region FD2 may be electrically connected to each other. In other words, the first to eighth transfer transistors may share the floating diffusion region FD. It will be understood that the first floating diffusion region FD1 and the second floating diffusion region FD2 may be collectively considered as a single floating diffusion region FD when the first and second diffusion regions FD1 and FD2 are electrically connected to each other .); and a first reset transistor that connects a first capacitor to the first floating diffusion region based on a first control signal ( Figs. 10-13, [0058]: reset transistor RG2 connected to the floating diffusion region FD and controlled by second reset control signal RX2 ), wherein each of the first to fourth pixels includes a first photoelectric conversion element, a first transfer transistor connected to the first photoelectric conversion element and the first floating diffusion region ( as illustrated by Fig. 13, PD1, TX1 and FD ), a second photoelectric conversion element, and a second transfer transistor connected to the second photoelectric conversion element and the first floating diffusion region ( as illustrated by Fig. 13, PD1, TX1 and FD ), wherein each of the fifth pixel and the sixth pixel includes a third photoelectric conversion element, a third transfer transistor connected to the third photoelectric conversion element and the second floating diffusion region, a fourth photoelectric conversion element, and a fourth transfer transistor connected to the fourth photoelectric conversion element and the second floating diffusion region ( Figs. 10-13, [0058]: each of pixel includes PD1-PD8, TX1-TX8 and FD ), wherein the first capacitor and the first reset transistor are each disposed in any one of the third to sixth pixels ( as illustrated by Fig. 11, [0090]-[0091]: reset transistor RG2 disposed in any of TR141 to TR144 ). YUN does not teach the first reset transistor that connects a first capacitor to the first floating diffusion region. However, CHOI discloses the first reset transistor ( as illustrated by Fig. 8A, [0082]: Dual conversion transistor DCX ) that connects a first capacitor ( as illustrated by Fig. 8A, [0082]: capacitance C RDC ) to the first floating diffusion region ( as illustrated by Fig. 8A, [0082]: Floating diffusion FD ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the first reset transistor that connects a first capacitor to the first floating diffusion region as taught by CHOI into YUN image sensor. The suggestion/ motivation for doing so would be to further increase the capacitance and thereby to increase a variable range of conversion gain ( CHOI : [0105]). YUN and CHOI combination does not teach wherein the first capacitor and the first reset transistor are each disposed in any one of the third to sixth pixels. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first capacitor and the first reset transistor are each disposed in any one of the third to sixth pixels , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse , 86 USPQ 70. Regarding claim 2 , YUN and CHOI combination teaches the image sensor of claim 1, except wherein the first capacitor is disposed inside the sixth pixel , and the first reset transistor is disposed inside the fourth pixel . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first capacitor is disposed inside the sixth pixel, and the first reset transistor is disposed inside the fourth pixel , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse , 86 USPQ 70. Regarding claim 3 , YUN and CHOI combination teaches the image sensor of claim 2, in addition YUN discloses further comprises: a first source-follower transistor ( as illustrated by Fig. 13, [0050]: SF driving transistor that is controlled by the floating diffusion region FD to generate an output voltage. The transistor SF is electrically connected to the floating diffusion region FD ); and a selection transistor (SEL) disposed inside the fifth pixel , a second reset transistor (RG1) disposed inside the fourth pixel ( as illustrated by Fig. 13, [0050]: SEL may be a selection transistor whose drain node connected to the source node of the transistor SF, and the transistor SEL controlled by a selection signal SX and may output the output voltage Vout to a column line CL connected to the unit pixel. ); In addition, CHOI further discloses a second source-follower transistor ( as illustrated by Fig. 8, [0065]: S2) disposed inside the third pixel , wherein gates of the first and second source-follower transistors ( as illustrated by Fig. 8, [0065]: SF1 and SF2) are electrically connected to the first floating diffusion region (FDC) and an active region of the first reset transistor ( as illustrated by Fig. 8A, [0065]: DCX), wherein the active region of the first reset transistor, the active region of the second reset transistor, and the active region of the first capacitor are electrically connected to one another ( as illustrated by Fig. 8, [0065]: DCX, RX and C RDC are electrically connected), and wherein the active regions of the first source-follower transistor and the second source-follower transistor are electrically connected to the active region of the selection transistor ( as illustrated by Fig. 8, [0065]: S1, S2 and SE are electrically connected). YUN and CHOI combination does not teach a selection transistor (SEL) disposed inside the fifth pixel , a second reset transistor (RG1) disposed inside the fourth pixel AND a second source-follower transistor disposed inside the third pixel . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a selection transistor disposed inside the fifth pixel , a second reset transistor disposed inside the fourth pixel AND a second source-follower transistor disposed inside the third pixel , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse , 86 USPQ 70 . 07-21-aia AIA Claim s 7-8, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over the YUN and CHOI combination as applied above, in view of Choi et al. (US 20230421921 A1, hereinafter “ Choi’921 ”), and further in view of court Case Law In re Japikse , 86 USPQ 70 . Regarding claim 7 , claim 7 has been analyzed and rejected with regard to claim 1 and in accordance with the YUN and CHOI combination, except a second reset transistor that connects a second capacitor, the first capacitor, and the first floating diffusion region based on a second control signal; wherein the first capacitor, the second capacitor, the first reset transistor and the second reset transistor are each disposed in any one of the third to sixth pixels. However, Choi’921 discloses a readout circuit including a second reset transistor that connects a second capacitor, the first capacitor, and the first floating diffusion region based on a second control signal (as illustrated by Fig. 2A, [0027]: LFG 230, capacitor 232, capacitor 228 and FD1 218 with control signal LFG 242). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second reset transistor that connects a second capacitor, the first capacitor, and the first floating diffusion region based on a second control signal as taught by Choi’921 into YUN and CHOI combination. The suggestion/ motivation for doing so would be to provide reduced image lag ( Choi’921 : [0011]). and furthermore It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first capacitor, the second capacitor, the first reset transistor and the second reset transistor are each disposed in any one of the third to sixth pixels , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse , 86 USPQ 70. Regarding claim 8 , YUN , CHOI and Choi’921 combination teaches the image sensor of claim 7, in addition It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first capacitor is disposed inside the fifth pixel, the second capacitor is disposed inside the sixth pixel, the first reset transistor is disposed inside the fourth pixel, and the second reset transistor is disposed inside the sixth pixel , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse , 86 USPQ 70. Regarding claim 19 , claim 19 has been analyzed with regard to claim 7 and is rejected for the same reasons of obviousness as used above. Regarding claim 20 , YUN , CHOI and Choi’921 combination teaches the image sensor of claim 19, in addition Choi’921 discloses wherein a capacitance of the second capacitor is greater than a capacitance of the first capacitor ( [0028]: The LOFIC 232 may have a capacitance higher than the first floating diffusion FD1 218 and the second capacitor 228. In one example, the capacitance (or charge storing capacity) of the first floating diffusion FD1 218 and the capacitance (or charge storing capacity) of the second capacitor 228 are configured to be the same. In another example, the capacitance of the first floating diffusion FD1 218 is configured to be less than the capacitance of the second capacitor 228. The LOFIC 232 may have a charge storage capacity greater than that of the photodiode 214 ). The suggestion/ motivation for doing so would be to increase high dynamic range capabilities of corresponding image sensors ( Choi’921 : [0015]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-6 and 9-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Contact 07-101 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204 . The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.usp to. gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000 . /ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638 Application/Control Number: 19/187,451 Page 2 Art Unit: 2638 Application/Control Number: 19/187,451 Page 3 Art Unit: 2638 Application/Control Number: 19/187,451 Page 4 Art Unit: 2638 Application/Control Number: 19/187,451 Page 5 Art Unit: 2638 Application/Control Number: 19/187,451 Page 6 Art Unit: 2638 Application/Control Number: 19/187,451 Page 7 Art Unit: 2638 Application/Control Number: 19/187,451 Page 8 Art Unit: 2638 Application/Control Number: 19/187,451 Page 9 Art Unit: 2638 Application/Control Number: 19/187,451 Page 10 Art Unit: 2638 Application/Control Number: 19/187,451 Page 11 Art Unit: 2638
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