Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 19/187,472 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
In response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
The instant Application No. 19187472 filed 04/23/2025 claims foreign priority to 10-2024-0125668, filed 09/13/2024.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 4/23/2025 and 10/10/2025 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy (copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-9, 11-13 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Blagodurov et al. (US 2022/0100668).
1. A shared memory device comprising: [Blagodurov teaches “[0033] Memory devices 102, 104, 108, and 110 are remote data storage agents that provide access to data in external memory pools via scalable data fabric 150 which is shared between multiple compute agents such as CPUs 122 and 124.”]
a memory bank configured to store first raw data corresponding to a first cache line stored in a first processor among a plurality of processors; [Blagodurov teaches “[0026] In some implementation, a data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory devices, and a scalable data fabric coupled to the host processor and to the plurality of remote memory devices, wherein the scalable data fabric comprises hardware control logic operative to track a number of cache line accesses to a page of memory associated with one or more of the plurality of remote memory devices, such as by updating a page probe filter entry field with data representing the tracked number of cache line accesses,” (see pars. 0023, 0033)]
a snoop filter circuit including a first snoop filter entry corresponding to the first cache line and a first entry access count corresponding to the first snoop filter entry; and [Blagodurov teaches “[0026]… the scalable data fabric comprises hardware control logic operative to track a number of cache line accesses to a page of memory associated with one or more of the plurality of remote memory devices, such as by updating a page probe filter entry field with data representing the tracked number of cache line accesses,” “[0039] Scalable data fabric 150 includes a set of one or more page probe filters 152. In the exemplary embodiment that will be described further below, page probe filters 152 store information indicating locations of data elements that are cached anywhere in the system, and other filters that track non-cacheable memory accesses. As set forth below, hardware control logic 153 with memory access spike detection is added as part of a page probe filter.” (see fig. 3 and related text; pars. 0054-0055, 0057-0058) “[0062] As shown by line 402 (FIG. 4) each DRAM access is tracked by the PPF 214 (per CS). As shown by line 524, control logic 525 updates the MMAC field 506 with tracked cache line access counts and other information (see e.g., Table 1).” “[0067] FIG. 6 is a flowchart illustrating one example of a method for monitoring memory access traffic. The operations may be performed in any suitable order. As shown in block 600 the method includes tracking, such as by the control logic 525 of the hardware control logic 153, a number of cache line accesses to a page of memory associated with one or more devices by updating a cache directory, such as the MMAC field, with data representing the tracked number of cache line accesses. For example, each time a CS checks a page probe filter to see if a cache line should be accessed from a page residing in memory, the control logic 525 updates the read or write counter accordingly.”]
a migration management circuit configured to determine a hotness of the first cache line based on the first entry access count and to issue a migration request for the first raw data to the first processor based on the hotness [Blagodurov teaches “[0026]… compare the data representing the tracked number of cache line accesses with a threshold indicating a number of cache line access counts signifying a spike in cache line accesses to a given page within a period of time, and produce spike indication data that signifies the spike in cache line accesses to a given the page of memory based on the data representing the tracked number of cache line accesses. In certain examples, the host processor moves the page to a faster memory based on the spike indication data.” “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.”].
2. The shared memory device of claim 1, wherein the migration management circuit is configured to determine the first cache line as a hot cache line when the first entry access count is greater than a hotness threshold value [Blagodurov teaches “[0054]… As shown by block 304, the method includes producing spike indication data that indicates a spike in cache line accesses to a given page of memory. In some examples this is done based on the data representing the tracked number of cache line accesses. The spike indication data may be, for example, data in a page probe filter entry field, a register pointer to data in memory, a hardware log entry, a notification in the form of an interrupt, or any other suitable mechanism. In some implementations when a spike is detected, the memory scheduler, such as the operating system in one example, moves the page from a slower memory to a faster memory based on the spike indication data. A spike in cache line access can be based on any suitable criteria. In one example, a spike is determined based on comparing a number of cache line accesses to a threshold value, such as a programmable threshold. In other implementations, the spike is determined based on comparing a number of cache line accesses that occur over a period of time, to a threshold value. The period of time in some examples is a programmable value stored in a register.” (see pars. 0024, 0026-0027, 0030, 0062, 0067)].
3. The shared memory device of claim 1, wherein the first entry access count is increased in response to an access for the first snoop filter entry from the plurality of processors [Blagodurov teaches “[0062] As shown by line 402 (FIG. 4) each DRAM access is tracked by the PPF 214 (per CS). As shown by line 524, control logic 525 updates the MMAC field 506 with tracked cache line access counts and other information (see e.g., Table 1).” “[0067] FIG. 6 is a flowchart illustrating one example of a method for monitoring memory access traffic. The operations may be performed in any suitable order. As shown in block 600 the method includes tracking, such as by the control logic 525 of the hardware control logic 153, a number of cache line accesses to a page of memory associated with one or more devices by updating a cache directory, such as the MMAC field, with data representing the tracked number of cache line accesses. For example, each time a CS checks a page probe filter to see if a cache line should be accessed from a page residing in memory, the control logic 525 updates the read or write counter accordingly.”].
4. The shared memory device of claim 3, further comprising: a back snoop circuit configured to update the first entry access count by repeatedly performing a back snoop operation for the first snoop filter entry [Blagodurov teaches “[0054]… a method for monitoring memory access traffic in a data processing system and in this example is carried out by hardware control logic 153. However, any other suitable hardware logic may also perform the operations described herein. In addition, the order of the operations may be any suitable order as desired. As shown in block 300, in some implementations, the hardware control logic 153 that in one example is part of the scalable data fabric 150 tracks a number of cache line accesses to a page of memory associated with one or more memory devices such as the remote memory devices 102, 104, 108 and 110. In one example, tracking is performed by updating, a cache directory, such as a page probe filter entry field, with data representing the tracked number of cache line accesses. As shown by block 304, the method includes producing spike indication data that indicates a spike in cache line accesses to a given page of memory. In some examples this is done based on the data representing the tracked number of cache line accesses. The spike indication data may be, for example, data in a page probe filter entry field, a register pointer to data in memory, a hardware log entry, a notification in the form of an interrupt, or any other suitable mechanism. In some implementations when a spike is detected, the memory scheduler, such as the operating system in one example, moves the page from a slower memory to a faster memory based on the spike indication data. A spike in cache line access can be based on any suitable criteria. In one example, a spike is determined based on comparing a number of cache line accesses to a threshold value, such as a programmable threshold. In other implementations, the spike is determined based on comparing a number of cache line accesses that occur over a period of time, to a threshold value. The period of time in some examples is a programmable value stored in a register.” “[0064] In some implementations, the control logic 525 upon reaching a predetermined access threshold 530 (set via a configuration register), updates the MMAC field and reports the number of reads and writes issued since the last reset to the log. The Configuration Registers 510 values can be set by the driver 131 (e.g., kernel). The configuration registers for the access threshold and spike threshold can be set to any suitable value depending upon the desired sensitivity.” “[0067]… If the count is exceeded, the current time stamp is recorded and the spike event is reported for the memory scheduler. For example, if the number of reads/ns and writes/ns to any cache lines since a last reset event the number detected over the past ms exceeds the numbers tracked per ns by 10×, a spike event is determined, and the current time stamp is recorded and the spike event is reported to the log.” (see table 1, par. 0068) where upon reset or back snoop, the hardware circuit continues updating the access count and determining spike events repeatedly].
7. The shared memory device of claim 1, wherein the migration management circuit is configured to issue the migration request, based on an entry eviction decision notification for the first snoop filter entry from the snoop filter circuit [Blagodurov teaches “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.” “[0065] If any of the spike conditions and/or access threshold conditions are met, the control logic 525 writes the (useful) contents of that PPF entry (e.g. PA, MMAC) to the kernel log reserved for the page access trace. The configuration register 512 point to the next available entry in the log (BEGIN). The PPF metadata may also be written to the trace buffer on PPF entry evictions (called downgrades)… [0070] In some implementations, the page probe filter keeps track of all pages currently resident in L3 memory in order to maintain cache coherence and tracks useful metadata about the sudden spikes in memory usage and page main-memory accesses: such as how many times a page has been accessed in main-memory. The page memory access metadata is periodically flushed to a log file accessible only by the memory scheduler. This includes access counts, physical addresses, and other potentially useful information. In some implementations, the metadata is written to a trace buffer on entry evictions (called downgrades). If there are suddenly many accesses to a given page, the PPF records the time stamp of the spike event and notifies the memory scheduler right away. The memory scheduler will set/reset the configuration registers which enable/disable the widget, point to the log file and perform other operations as described above.”].
8. The shared memory device of claim 1, wherein the first processor is configured to migrate the first raw data to a dedicated memory device for the first processor based on the migration request [Blagodurov teaches “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.” “[0044] Driver 131 periodically scans active page table 148 and uses the data from a log file that includes spike indication data, cache line access count data and other data as described below to determine what pages are candidates for data movement to faster memory. For example, data movement candidates could be data currently cached in slow non-volatile RAM (NVRAM) or memory in extended scalable fabric system 200. In some implementations instead of the memory controller 132 moving pages, the scalable fabric 150 includes a DMA engine that utilizes a predetermined system call, e.g. the “movepage” system call, to migrate the pages to local memory 146. In other implementations, the operating system controls movement of pages from a current memory that is slow to a faster memory.”].
9. The shared memory device of claim 8, wherein: the memory bank includes a first physical page including the first raw data, and the first processor is configured to migrate the first physical page to the dedicated memory device based on the migration request [The rationale in the rejection of claim 8 is herein incorporated].
11. A memory system comprising: a first processor including a cache memory that stores a plurality of cache lines; a dedicated memory device for the first processor; and a shared memory device configured to store a raw data for a first cache line of the plurality of cache lines, and to determine whether the first cache line is a hot cache line, wherein the first processor is configured to migrate the raw data from the shared memory device to the dedicated memory device when the first cache line is determined to be the hot cache line [The rationale in the rejection of claim 1 is herein incorporated. Note Blagodurov teaches “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.” Where local memory corresponds to the claimed dedicated memory device].
12. The memory system of claim 11, wherein the shared memory device includes: a snoop filter circuit configured to store a plurality of snoop filter entries respectively corresponding to the plurality of cache lines and a plurality of entry access counts respectively corresponding to the plurality of snoop filter entries, and to increase each of the plurality of entry access counts based on an entry access occurrence for a corresponding snoop filter entry; and a migration management circuit configured to determine whether the first cache line is the hot cache line by comparing a first entry access count that corresponds to the first cache line, with a hotness threshold value [Blagodurov teaches “[0026]… compare the data representing the tracked number of cache line accesses with a threshold indicating a number of cache line access counts signifying a spike in cache line accesses to a given page within a period of time, and produce spike indication data that signifies the spike in cache line accesses to a given the page of memory based on the data representing the tracked number of cache line accesses. In certain examples, the host processor moves the page to a faster memory based on the spike indication data.” “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.” “[0054]… As shown by block 304, the method includes producing spike indication data that indicates a spike in cache line accesses to a given page of memory. In some examples this is done based on the data representing the tracked number of cache line accesses. The spike indication data may be, for example, data in a page probe filter entry field, a register pointer to data in memory, a hardware log entry, a notification in the form of an interrupt, or any other suitable mechanism. In some implementations when a spike is detected, the memory scheduler, such as the operating system in one example, moves the page from a slower memory to a faster memory based on the spike indication data. A spike in cache line access can be based on any suitable criteria. In one example, a spike is determined based on comparing a number of cache line accesses to a threshold value, such as a programmable threshold. In other implementations, the spike is determined based on comparing a number of cache line accesses that occur over a period of time, to a threshold value. The period of time in some examples is a programmable value stored in a register.” (see pars. 0024, 0027, 0030) “[0062] As shown by line 402 (FIG. 4) each DRAM access is tracked by the PPF 214 (per CS). As shown by line 524, control logic 525 updates the MMAC field 506 with tracked cache line access counts and other information (see e.g., Table 1).” “[0067] FIG. 6 is a flowchart illustrating one example of a method for monitoring memory access traffic. The operations may be performed in any suitable order. As shown in block 600 the method includes tracking, such as by the control logic 525 of the hardware control logic 153, a number of cache line accesses to a page of memory associated with one or more devices by updating a cache directory, such as the MMAC field, with data representing the tracked number of cache line accesses. For example, each time a CS checks a page probe filter to see if a cache line should be accessed from a page residing in memory, the control logic 525 updates the read or write counter accordingly.” (see par. 0067)].
13. The memory system of claim 12, wherein the shared memory device further includes: a back snoop circuit configured to update the first entry access count by repeatedly performing a back snoop operation for a first snoop filter entry that corresponds to the first cache line [The rationale in the rejection of claim 4 is herein incorporated].
16. The memory system of claim 12, wherein the migration management circuit is configured to issue a migration request for the raw data to the first processor when the first cache line is determined as the hot cache line [The rationale in the rejection of claim 8 is herein incorporated].
17. The memory system of claim 12, wherein the migration management circuit is configured to: issue a migration request for the raw data after an entry eviction decision notification for a first snoop filter entry that correspond to the first cache line is received from the snoop filter circuit [The rationale in the rejection of claim 8 is herein incorporated].
18. The memory system of claim 12, wherein the first processor is configured to adjust the hotness threshold value based on an occurrence frequency of a migration request from the shared memory device [Blagodurov teaches “[0021] In certain examples, the method includes setting one or more configuration registers with data representing at least one of: a threshold cache line read access rate that constitutes a memory usage spike; a threshold cache line write access rate that constitutes a memory usage spike; a threshold for a length of time that cache line accesses have to continually spike; a pointer to log that contains spike indication data; and enabling a spike detection mode.” “[0054]… In one example, a spike is determined based on comparing a number of cache line accesses to a threshold value, such as a programmable threshold. In other implementations, the spike is determined based on comparing a number of cache line accesses that occur over a period of time, to a threshold value. The period of time in some examples is a programmable value stored in a register.” “[0061]… he PPF 214 includes a set of configuration registers (CRs) 510 available to the memory scheduler or other suitable configuration mechanism are used, including one or more registers 512 that set the log file location, reset 514 the configuration registers (CRs) 510, set 516 an access threshold 530 for reporting, enable/disable 518 the spiked page access trace operation (for example when implemented as an extension), set a spike threshold 520 and set a time period through a timer 522. In addition to MMAC thresholds and pointers to the log, the control registers can include other control registers for controlling timing information or other useful control operations. As such, the configuration registers, in some examples, contain data representing at least one or more of a threshold cache line read access rate that constitutes a memory usage spike, a threshold cache line write access rate that constitutes a memory usage spike, a threshold for a length of time that cache line accesses have to continually spike, a pointer to a log that contains spike indication data and enabling a spike detection mode.” “[0064] In some implementations, the control logic 525 upon reaching a predetermined access threshold 530 (set via a configuration register), updates the MMAC field and reports the number of reads and writes issued since the last reset to the log. The Configuration Registers 510 values can be set by the driver 131 (e.g., kernel). The configuration registers for the access threshold and spike threshold can be set to any suitable value depending upon the desired sensitivity.”].
19. A shared memory device configured to communicate with a first processor which stores a first cache line, the shared memory device comprising: [Blagodurov teaches “[0033] Memory devices 102, 104, 108, and 110 are remote data storage agents that provide access to data in external memory pools via scalable data fabric 150 which is shared between multiple compute agents such as CPUs 122 and 124.”]
a snoop filter circuit including a snoop filter entry for the first cache line, and an entry access count for the snoop filter entry; [Blagodurov teaches “[0026]… the scalable data fabric comprises hardware control logic operative to track a number of cache line accesses to a page of memory associated with one or more of the plurality of remote memory devices, such as by updating a page probe filter entry field with data representing the tracked number of cache line accesses,” “[0039] Scalable data fabric 150 includes a set of one or more page probe filters 152. In the exemplary embodiment that will be described further below, page probe filters 152 store information indicating locations of data elements that are cached anywhere in the system, and other filters that track non-cacheable memory accesses. As set forth below, hardware control logic 153 with memory access spike detection is added as part of a page probe filter.” (see fig. 3 and related text; pars. 0054-0055, 0057-0058) “[0062] As shown by line 402 (FIG. 4) each DRAM access is tracked by the PPF 214 (per CS). As shown by line 524, control logic 525 updates the MMAC field 506 with tracked cache line access counts and other information (see e.g., Table 1).” “[0067] FIG. 6 is a flowchart illustrating one example of a method for monitoring memory access traffic. The operations may be performed in any suitable order. As shown in block 600 the method includes tracking, such as by the control logic 525 of the hardware control logic 153, a number of cache line accesses to a page of memory associated with one or more devices by updating a cache directory, such as the MMAC field, with data representing the tracked number of cache line accesses. For example, each time a CS checks a page probe filter to see if a cache line should be accessed from a page residing in memory, the control logic 525 updates the read or write counter accordingly.”]
a back snoop circuit configured to update the entry access count by performing a back snooping for the first cache line; and [Blagodurov teaches “[0054]… a method for monitoring memory access traffic in a data processing system and in this example is carried out by hardware control logic 153. However, any other suitable hardware logic may also perform the operations described herein. In addition, the order of the operations may be any suitable order as desired. As shown in block 300, in some implementations, the hardware control logic 153 that in one example is part of the scalable data fabric 150 tracks a number of cache line accesses to a page of memory associated with one or more memory devices such as the remote memory devices 102, 104, 108 and 110. In one example, tracking is performed by updating, a cache directory, such as a page probe filter entry field, with data representing the tracked number of cache line accesses. As shown by block 304, the method includes producing spike indication data that indicates a spike in cache line accesses to a given page of memory. In some examples this is done based on the data representing the tracked number of cache line accesses. The spike indication data may be, for example, data in a page probe filter entry field, a register pointer to data in memory, a hardware log entry, a notification in the form of an interrupt, or any other suitable mechanism. In some implementations when a spike is detected, the memory scheduler, such as the operating system in one example, moves the page from a slower memory to a faster memory based on the spike indication data. A spike in cache line access can be based on any suitable criteria. In one example, a spike is determined based on comparing a number of cache line accesses to a threshold value, such as a programmable threshold. In other implementations, the spike is determined based on comparing a number of cache line accesses that occur over a period of time, to a threshold value. The period of time in some examples is a programmable value stored in a register.” “[0064] In some implementations, the control logic 525 upon reaching a predetermined access threshold 530 (set via a configuration register), updates the MMAC field and reports the number of reads and writes issued since the last reset to the log. The Configuration Registers 510 values can be set by the driver 131 (e.g., kernel). The configuration registers for the access threshold and spike threshold can be set to any suitable value depending upon the desired sensitivity.” “[0067]… If the count is exceeded, the current time stamp is recorded and the spike event is reported for the memory scheduler. For example, if the number of reads/ns and writes/ns to any cache lines since a last reset event the number detected over the past ms exceeds the numbers tracked per ns by 10×, a spike event is determined, and the current time stamp is recorded and the spike event is reported to the log.” (see table 1, par. 0068) where upon reset or back snoop, the hardware circuit continues updating the access count and determining spike events]
a migration management circuit configured to determine a hotness of the first cache line based on the entry access count [Blagodurov teaches “[0026]… compare the data representing the tracked number of cache line accesses with a threshold indicating a number of cache line access counts signifying a spike in cache line accesses to a given page within a period of time, and produce spike indication data that signifies the spike in cache line accesses to a given the page of memory based on the data representing the tracked number of cache line accesses. In certain examples, the host processor moves the page to a faster memory based on the spike indication data.” “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Blagodurov et al. (US 2022/0100668) in view of Blagodurov et al. (US 10,235,290), hereinafter (Blagodurov’290).
10. The shared memory device of claim 9, wherein: the first processor includes one or more cache lines in addition to the first cache line, the first physical page is configured to store one or more raw data respectively corresponding to the one or more cache lines, and the migration management circuit is configured to: [Blagodurov teaches “[0018]… the tracked number of cache line accesses includes a count of read accesses and a count of write accesses issued to cache lines within a page of memory: (a) since a movement of data from the page probe filter entry to a log, such as a data file, and (b) over a defined time period to detect access spikes.” ]
determine a hotness of each of the one or more cache lines, determine a number of cache lines that are hot cache lines among the first cache line and the one or more cache lines, based on the hotness of the first cache line and the hotness of each of the one or more cache lines, and [Blagodurov teaches “[0040] In the illustrated embodiment, driver 131 runs on CPU 122 and periodically scans active page table 148 and a log file (e.g., that includes spike indication data and cache line access count information) to determine which pages being accessed by CPU 122 and 124 are currently stored in a slower or more remote memory, e.g. one of memory devices 102, 104, 108, and 110, or slower memories within the local memory and utilizes a system call known as “movepage” to migrate selected pages to local memory 146. In some implementations, the driver 131 and the memory controller move pages between the memory devices 102, 104, 108 and 110. In certain implementations where the local memory is made of up different types of memory devices (some slower and others faster) pages are moved within the local memory. Thus, driver 131 in conjunction with the memory controller 132 opportunistically moves data to improve the locality of data placement in a system with a complex, scalable data fabric.” “[0044] Driver 131 periodically scans active page table 148 and uses the data from a log file that includes spike indication data, cache line access count data and other data as described below to determine what pages are candidates for data movement to faster memory. For example, data movement candidates could be data currently cached in slow non-volatile RAM (NVRAM) or memory in extended scalable fabric system 200. In some implementations instead of the memory controller 132 moving pages, the scalable fabric 150 includes a DMA engine that utilizes a predetermined system call, e.g. the “movepage” system call, to migrate the pages to local memory 146. In other implementations, the operating system controls movement of pages from a current memory that is slow to a faster memory.”] where data is migrated for a page of cache lines but Blagodurov does not expressly disclose issue the migration request when the number of cache lines is greater than a migration threshold value; however, regarding these limitations, *** teaches; however, regarding these limitations, Blogadurov’290 teaches [“ the Hot Bit marks those pages that were accessed at least q times, where q is a configurable kernel parameter. At the end of the interval, all pages that had more than q memory accesses will have their respective accessed/hot bits set in the PTE. These now may form the hot set of pages. Similar to FTHP, if the hot set is smaller than N, then a first-touch policy may be utilized to populate the remainder of the fast memory. If the hot set is larger than N, then the fast memory may be populated by the first N pages. The first N pages can be chosen based on a first-come, first-served (FCFS)/first-in, first-out (FIFO) order or, if the pages are stored in a hot set indexed by the physical address, the pages with the smallest or largest physical addresses.” (col. 9, lines 11-23) “ Turning now to FIG. 4, a block diagram of one embodiment of performing a time series analysis 400 for dynamically adjusting the hot set is shown. In one embodiment, a controller may be configured to perform generalized hot set adjustment to continuously observe the hot set of pages the system brings into the faster levels of memory and then refine one or more control parameters in an attempt to influence the future hot set. The controller may be implemented using any combination of software and/or hardware, depending on the embodiment. Each memory region A, B, and N is intended to represent a memory region which is being monitored by the controller. In one embodiment, the size of each memory region may be a page, while in other embodiments, other sizes of memory regions may be utilized. “ (col. 10, lines 56-col. 11, line 9)].
Blagodurov and Blagodurov’290 are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Blagodurov to issue the migration request when the number of cache lines or regions is greater than a migration threshold value as taught by Blagodurov’290 since doing so would provide benefits as [“some number of hot pages are pre-loaded into the first-level memory to reduce faults, and the remaining first-level memory capacity can be populated dynamically based on whichever pages the program accesses.” (col. 8, lines 40-43)].
Therefore, it would have been obvious to combine Blagodurov and Blagodurov’290 for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Lam et al. (US 2016/0306741) teaches “An on-chip memory in a many-core system is partitioned, and according to a frequency at which a processor core set in each on-chip partition accesses a virtual memory page in virtual memory space that is shared among multiple processes that belong to a same application program, data corresponding to the virtual memory page is moved to an on-chip memory partition in which a processor core set whose access frequency is high is located such that when the virtual memory page is subsequently accessed, a time delay caused by cross-partition access is reduced.” (Abstract).
Ray et al. (US 2021/0049101) teaches “A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.” (Abstract).
Iwamitsu et al. (US 2014/0108759) teaches “A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.” (Abstract).
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 7-13, 16-19 have received a first action on the merits and are subject of a first action non-final.
a(2) ALLOWABLE SUBJECT MATTER
Per the instant office action, claims 5, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. The shared memory device of claim 4, wherein the back snoop circuit is configured to: provide an invalidation request for the first cache line to the first processor at a first time point within a first time period when the back snoop operation is performed; and increase the first entry access count when the access for the first snoop filter entry occurs between the first time point and a second time point at which a back snoop test time has elapsed from the first time point.
14. The memory system of claim 13, wherein the back snoop circuit is configured to: provide an invalidation request for the first cache line to the first processor at a first time point within a first time period when the back snoop operation is performed; and increase the first entry access count when an access for the first snoop filter entry occurs between the first time point and a second time point at which a back snoop time has elapsed from the first time point.
20. The shared memory device of claim 19, wherein the back snoop circuit is configured to 1.
Claims 6 and 15 are objected to by virtue of their dependence on objected claims 5 and 14 respectively.
6. The shared memory device of claim 5, wherein the back snoop circuit is configured to invalidate the first snoop filter entry based on the access for the first snoop filter entry not occurring between the first time point and the second time point.
15. The memory system of claim 14, wherein the back snoop circuit is configured to: invalidate the first snoop filter entry based on the access for the first snoop filter entry not occurring between the first time point and the second time point.
b. DIRECTION OF FUTURE CORRESPONDENCES
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September 1, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
