Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5-6, 8-12, 15-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. Pub. No. US 2018/0075808 A1 [Yamashita] in view of Kwan et al. Pub. No. US 2009/0027364 A1 [Kwan].
1. Yamashita discloses a display system [Fig. 2] for driving pixels of a pixel array [28], the display system comprising:
display driver circuitry [20a] configured to: receive image frame data comprising a plurality of frame zones [Fig. 9], each frame zone comprising:
intensity values for a plurality of bit planes [¶ 72]; and
process the image frame data to determine, for at least one pixel of the pixel array, a pixel drive value and a pixel drive time interval for each bit plane of the plurality of bit planes of at least one frame zone corresponding to the at least one pixel [¶ 128]; and
a display backplane [¶ 45] comprising:
pixel driver circuitry comprising a pixel circuit to drive the at least one pixel of the pixel array such that an intensity of the at least one pixel varies for each bit plane according to the corresponding pixel drive value and the corresponding pixel drive time interval [¶ 72].
Yamashita is silent on the global bias feature.
However, Kwan teaches a display driving circuit [Fig. 5] with a global timing circuit [512]. As described in paragraph 116 and throughout, the “global timing control unit 512 receives operational codes ("opcodes") from a system (not shown), decodes the opcodes into operational instructions, and asserts operational instructions (e.g., no-op instructions, data write commands, load row address commands, etc.) on bus 513 to administer the global operations of display system 500.” This global timing system controls the display driver, i.e., biases, the image producing pixels [see Fig. 5 where this carried out by 516 to 504(r), 504(g) and 504(b)].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita with Kwan to have this global bias feature, since such a modification optimizes image quality while minimizing power usage which is a long-felt need in the art.
2. Yamashita in view of Kwan teaches wherein: the pixel drive value comprises a pixel drive voltage or a pixel drive current [Yamashita ¶¶ 6-10 where gate/scan drivers output currents].
5. Yamashita in view of Kwan teaches a sequence memory for storing one or more programmable mappings that modify at least one of the pixel drive value and the pixel drive time interval based on at least one of: desired performance, ambient lighting compensation, or temperature compensation [Kwan ¶ 371 where memory mapping is necessary].
6. Yamashita in view of Kwan teaches wherein the display driver circuitry converts at least one of the pixel drive values or the pixel drive time intervals according to the programmable mappings [where memory mapping is necessary in the modified invention].
8. Yamashita in view of Kwan teaches wherein the image frame data is received from an image or video data source comprising one or more of an image, image data, or a video source [Yamashita ¶ 45 display images].
9. Yamashita in view of Kwan is silent on wherein the image frame data is received from a host, said host comprising a processor that executes applications stored on or streamed to the host. However, the examiner takes official notice that it is notoriously old and well known to a person of ordinary skill in the art to have a host, e.g., a server, as required, since such a modification provides for improvements in the usability of the device.
10. Yamashita in view of Kwan teaches wherein: the pixels comprise light emitting diodes; and the pixel drive values comprise pixel drive currents [Yamashita ¶ 6, for instance].
11. Yamashita in view of Kwan teaches wherein: the pixels comprise liquid crystal on silicon; and the pixel drive values comprise voltages [Yamashita ¶ 83].
12. Yamashita in view of Kwan teaches wherein at least one of the display backplane or the display driver circuitry is an integrated circuit [Kwan ¶ 3].
15. Yamashita discloses a method of driving pixels of a pixel array [Figs. 1-2], the method comprising:
receiving image frame data comprising a plurality of frame zones [Fig. 9], each frame zone comprising:
intensity values for a plurality of bit planes [¶ 72];
processing the image frame data to determine, for at least one pixel of the pixel array, a pixel drive value and a pixel drive time interval for each bit plane of the plurality of bit planes of at least one frame zone corresponding to the at least one pixel [¶ 128]; and
driving the at least one pixel of the pixel array such that an intensity of the at least one pixel varies for each bit plane according to the corresponding pixel drive value and the corresponding pixel drive time interval [¶ 72].
Yamashita is silent on the global bias feature.
However, Kwan teaches a display driving circuit [Fig. 5] with a global timing circuit [512]. As described in paragraph 116 and throughout, the “global timing control unit 512 receives operational codes ("opcodes") from a system (not shown), decodes the opcodes into operational instructions, and asserts operational instructions (e.g., no-op instructions, data write commands, load row address commands, etc.) on bus 513 to administer the global operations of display system 500.” This global timing system controls the display driver, i.e., biases, the image producing pixels [see Fig. 5 where this carried out by 516 to 504(r), 504(g) and 504(b)].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita with Kwan to have this global bias feature, since such a modification optimizes image quality while minimizing power usage which is a long-felt need in the art.
16. Yamashita in view of Kwan teaches wherein: the pixel drive value comprises a pixel drive voltage or a pixel drive current [Yamashita ¶¶ 6-10 where gate/scan drivers output currents].
20. Yamashita discloses a device [Fig. 2] comprising:
a pixel array [28];
display driver circuitry [20a] configured to: receive image frame data comprising a plurality of frame zones [Fig. 9], each frame zone comprising:
intensity values for a plurality of bit planes [¶ 72]; and process the image frame data to determine, for at least one pixel of the pixel array, a pixel drive value and a pixel drive time interval for each bit plane of the plurality of bit planes of at least one frame zone corresponding to the at least one pixel [¶ 128]; and
a display backplane comprising: pixel driver circuitry comprising a pixel circuit to drive the at least one pixel of the pixel array such that an intensity of the at least one pixel varies for each bit plane according to the corresponding pixel drive value and the corresponding pixel drive time interval [¶ 72].
Yamashita is silent on the global bias feature.
However, Kwan teaches a display driving circuit [Fig. 5] with a global timing circuit [512]. As described in paragraph 116 and throughout, the “global timing control unit 512 receives operational codes ("opcodes") from a system (not shown), decodes the opcodes into operational instructions, and asserts operational instructions (e.g., no-op instructions, data write commands, load row address commands, etc.) on bus 513 to administer the global operations of display system 500.” This global timing system controls the display driver, i.e., biases, the image producing pixels [see Fig. 5 where this carried out by 516 to 504(r), 504(g) and 504(b)].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita with Kwan to have this global bias feature, since such a modification optimizes image quality while minimizing power usage which is a long-felt need in the art.
Claim(s) 3-4 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. Pub. No. US 2018/0075808 A1 [Yamashita] in view of Kwan et al. Pub. No. US 2009/0027364 A1 [Kwan] and further in view of Iverson et al. Pub. No. US 2021/0210046 A1 [Iverson].
3. Yamashita in view of Kwan is silent on a digital to analog converter driven by a register for converting a digital control word into a bias voltage to control a drive current of the pixel driver circuitry for all pixels of the pixel array. However Iverson teaches a digital to analog converter driven by a register for converting a digital control word into a bias voltage to control a drive current of the pixel driver circuitry for all pixels of the pixel array [¶¶ 42-43 information to drive colors]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita in view of Kwan with Iverson, since such a modification optimizes circuit performance.
4. Yamashita in view of Kwan and further in view of Iverson teaches wherein the display backplane includes circuitry that provides both bit plane digital data and the bias voltage to the pixel driver circuitry for driving all pixels of the pixel array [Iverson ¶ 26 where some circuitry is necessary for pixels].
17. Yamashita in view of Kwan is silent on converting a digital control word into a bias voltage to control a drive current for all pixels of the pixel array. However Iverson teaches converting a digital control word into a bias voltage to control a drive current for all pixels of the pixel array [¶¶ 42-43 information to drive colors]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita in view of Kwan with Iverson, since such a modification optimizes circuit performance.
18. Yamashita in view of Kwan and further in view of Iverson teaches driving all pixels of the pixel array in accordance with both bit plane digital data and the bias voltage [Iverson ¶ 26 where some circuitry is necessary for pixels].
Allowable Subject Matter
Claims 7, 13-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
7. The frame zone limitations in combination with each and every other limitation and when rewritten as detailed above make the claim allowable over the prior art of record.
13. The deactivate limitations in combination with each and every other limitation and when rewritten as detailed above make the claim allowable over the prior art of record.
19. See reasons for claim 7.
Response to Arguments
Applicant's arguments filed 4/22/2026 have been fully considered but they are not persuasive.
The applicant argues:
Prior art fails to teach “a global bias” as claimed, specifically citing that Kwan’s global clock is not equivalent to the global bias of the claimed invention. The examiner respectfully disagrees. The claimed limitation does not include any details of structure, function, or implementation, thereby strict definitions of global bias as argued by the applicant may not apply for the art in question. Thus, Kwan’s global satisfies the immensely broad claim of “a global bias.”
Prior art fails to teach a “pixel drive mechanism” with the claimed arrangement, specifically Kwan’s pixels are operated on binary voltage states either HIGH or LOW, and generate intensity through pulse width or pulse number modulation. The examiner does not contend the applicant’s analysis of Kwan; however, the examiner would like to note that this satisfies the broad driving as claimed. Just because initial driving has only two discrete pulse values HIGH and LOW does not mean that intensity is not a factor, in fact it reinforces it. When the pulse is HIGH, the pixel is displaying, when the pulse is LOW the pixel is not displaying, thus inherently the pixel intensity is based on of total HIGH in a particular time period and a total LOW in a particular time period. The applicant never claims that the display intensity is based solely on the magnitude of the pulse, but merely that the “intensity of the at least one pixel varies for each bit plane” which is clearly satisfied by Kwan.
The combination of Yamashita in view of Kwan therefore also satisfies the global bias limitation as well as the pixel intensity limitations as claimed.
For the reasons above, the art rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KE XIAO/SPE, Art Unit 2627
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