Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-12 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “determine a transmission interval of a target status read command, which is a status read command for identifying a processing result of the second read command, differently based on whether the memory is in an internal busy state or the internal ready state when the second read command is present”. The recited phrase “ differently based on whether the memory is in an internal busy state or the internal ready state when the second read command is present” fails to show a clear relation with the rest of the claim “determine a transmission interval of a target status read command, which is a status read command for identifying a processing result of the second read command”.
It is unclear how the phrase is related with the rest of the “determine” phrase in the claim.
Claim 8, repeating the feature as addressed above, is therefore rejected under the same assumption.
Dependent claims 2-7 and 9-12 are also rejected by virtue of their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20210181985 A1 (SHIN) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to claim 1, SHIN teaches storage device, comprising: a memory including a plurality of memory blocks (storage device 50 including memory device 100 arranged in plurality of memory cells configured to store data as plurality of memory blocks) [Fig. 1; Par. 0032-0035] and a cache for caching data read from the plurality of memory blocks (the storage device further including a buffer memory used as an operating memory or a cache memory to temporarily store system data for controlling the memory device) [Par. 0053-0056]; and a controller configured to: transmit a first read command to the memory, requesting to cache first data to the cache, when the memory is determined to be in an internal ready state (memory controller for controlling the memory device in the buffer memory and generating read commands based on status information indicating that the memory device is in a ready status is received) [Fig. 14; Par. 0048-0051; Par. 0006-0007]; transmit a data output command to the memory, requesting to output the first data, when the memory is determined to be in an external ready state after transmitting the first read command (the memory controller generating output signal to output, during a read operation corresponding to a read command received allowing the memory device to perform the read operation read data corresponding to the read operation if the status information indicating that the memory device a ready status is received) [Par. 0006-0007; Par. 0049-0053]; determine whether a second read command, requesting to cache second data to the cache, is present after receiving the first data output from the memory (after sensing the read data corresponding to the read operation the memory controller through command generator output a subsequent read command to the memory device) [Par. 0006-009; Par. 0049-0052]; and determine a transmission interval of a target status read command, which is a status read command for identifying a processing result of the second read command, based on whether the memory is in an internal busy state or the internal ready state when the second read command is present (memory controller to reference busy/ready status and determine, based on the read/busy signal, an operation end time indicating the time it takes to perform subsequent read operation [Fig. 11; Par. 0108-0114]; for an operation performed on the memory device, it is assumed that tR is the time it takes to transmit data from the memory cell array to the page buffer group, and Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device (Par. 0131; Par. 0126)]; the memory controller to determine the status of the memory device and then determine whether to output a subsequent command such that: if the memory device is in the ready status, the memory controller may output a command for performing a subsequent operation to the memory device; If the memory device is in the busy status, the memory controller may check the status of the memory device by outputting the status check command to the memory device until the memory device enters the ready status) [Fig. 11; Par. 0120-0127].
With respect to claim 2, SHIN teaches the storage device, wherein the memory is set to the internal busy state when data is being cached from one or more of the plurality of memory blocks to the cache [if the memory device 100 starts a read operation, the read/busy signal output from the memory device 100 may be in a low status; in other words, at t1, the memory device 100 may start the read operation, and the read/busy signal output from the memory device 100 may be in the low status (Par. 0113), ready/busy signal having a low status may indicate that the memory device 100 is in a busy status (Par. 0110; Fig. 5)], and is set to the internal ready state when no data is being cached from the plurality of memory blocks to the cache [a ready/busy signal having a low status may indicate that the memory device 100 is in a busy status (Par. 0110, Fig. 5)].
With respect to claim 3, SHIN teaches the storage device, wherein the controller is further configured to: transmit a status read command to the memory [signal output through the ready/busy line based on an operation which is performed by the memory device (Fig. 5; Par. 0109)]; and determine whether the memory is in the internal ready state based on an internal busy bit included in a response to the status read command [the memory controller to determine, based on the read/busy bit signal (Par. 0108; Par. 0083-0084)].
With respect to claim 4, SHIN teaches the storage device, wherein the memory is set to an external busy state when data is being output to the controller or received from the controller (the memory device may be in an externally busy status (EXTERNAL BUSY) during a period from t1 to td, only until transfer of data from the memory cell array to the page buffer group is completed (Fig. 6; Par. 0124)], and is set to the external ready state when data is neither being output to the controller nor received from the controller (only until transfer of data from the memory cell array to the page buffer group is completed, the memory device 100 may be in the busy status, i.e., after time td, the memory device may be in the ready status (Fig. 6; Par. 0124)].
With respect to claim 5, SHIN teaches the storage device, wherein the controller is further configured to: transmit a status read command to the memory; and determine whether the memory is in the external ready state based on an external busy bit included in a response to the status read command (status check read being ready/busy signal which is output from the memory device during the read period from t1 to td and the memory device being in an externally busy status (EXTERNAL BUSY) during a period from t1 to td check the status of the memory device (Par. 0124-0126)].
With respect to claim 6, SHIN teaches the storage device, wherein the controller is configured to: determine the transmission interval of the target status read command as a first interval when the memory is in the internal busy state; and determine the transmission interval of the target status read command as a second interval when the memory is in the internal ready state [for an operation performed on the memory device, tR is the time it takes to transmit data from the memory cell array to the page buffer group, and Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device (Par. 0131; Par. 0126)].
With respect to claim 7, SHIN teaches the storage device, wherein the second interval is longer than the first interval [Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device longer to tR being the time it takes to transmit data from the memory cell array to the page buffer group (Par. 0131; Par. 0126)].
With respect to claim 8, SHIN teaches method for operating a storage device, the method comprising: transmitting a first read command to a memory, including a cache for caching data read from a plurality of memory blocks, when the memory is determined to be in an internal ready state, the first read command requesting to cache first data in the cache (memory controller for controlling a memory device including a buffer memory and generating read commands based on status information indicating that the memory device is in a ready status is received) [Fig. 14; Par. 0048-0051; Par. 0006-0007]; transmitting a data output command to the memory, requesting to output the first data, when the memory is determined to be in an external ready state after transmitting the first read command (the memory controller generating output signal to output, during a read operation corresponding to a read command received allowing the memory device to perform the read operation read data corresponding to the read operation if the status information indicating that the memory device a ready status is received) [Par. 0006-0007; Par. 0049-0053]; receiving the first data output from the memory; determining whether a second read command, requesting to cache second data to the cache, is present after receiving the first data (after sensing the read data corresponding to the read operation the memory controller through command generator output a subsequent read command to the memory device) [Par. 0006-009; Par. 0049-0052]; and determining a transmission interval of a target status read command, which is a status read command for identifying a processing result of the second read command, differently based on whether the memory is in an internal busy state or the internal ready state when the second read command is present (memory controller to reference busy/ready status and determine, based on the read/busy signal, an operation end time indicating the time it takes to perform subsequent read operation [Fig. 11; Par. 0108-0114]; for an operation performed on the memory device, it is assumed that tR is the time it takes to transmit data from the memory cell array to the page buffer group, and Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device (Par. 0131; Par. 0126)].
With respect to claim 9, SHIN teaches method for operating a storage device, wherein transmitting the first read command to the memory includes: determining that the memory is in the internal busy state when data is being cached from one or more of the plurality of memory blocks to the cache [if the memory device 100 starts a read operation, the read/busy signal output from the memory device 100 may be in a low status; in other words, at t1, the memory device 100 may start the read operation, and the read/busy signal output from the memory device 100 may be in the low status (Par. 0113), ready/busy signal having a low status may indicate that the memory device 100 is in a busy status (Par. 0110; Fig. 5)]; and determining that the memory is in the internal ready state when no data is being cached from the plurality of memory blocks to the cache [a ready/busy signal having a low status may indicate that the memory device 100 is in a busy status (Par. 0110, Fig. 5)].
With respect to claim 10, SHIN teaches method for operating a storage device, wherein transmitting the data output command to the memory includes: determining that the memory is in an external busy state when the memory is outputting data or receiving data; and determining that the memory is in an external ready state when the memory is neither outputting data nor receiving data (status check read being ready/busy signal which is output from the memory device during the read period from t1 to td and the memory device being in an externally busy status (EXTERNAL BUSY) during a period from t1 to td check the status of the memory device (Par. 0124-0126)].
With respect to claim 11, SHIN teaches method for operating a storage device, wherein determining the transmission interval of the target status read command includes: determining the transmission interval of the target status read command as a first interval when the memory is in the internal busy state; and determining the transmission interval of the target status read command as a second interval when the memory is in the internal ready state [for an operation performed on the memory device, tR is the time it takes to transmit data from the memory cell array to the page buffer group, and Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device (Par. 0131; Par. 0126)].
With respect to claim 12, SHIN teaches method for operating a storage device, wherein the second interval is longer than the first interval [Tx is the data output time including both the time it takes to output data transmitted to the page buffer group to the memory controller and the time it takes to check the status of the memory device longer to tR being the time it takes to transmit data from the memory cell array to the page buffer group (Par. 0131; Par. 0126)].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240248643 (PARK) teaching operating method of a storage device including: receiving, by each of a plurality of memory devices, a first command, from a memory controller; outputting, by each of the plurality of memory devices, status data indicating whether a corresponding memory device is in a ready state or a busy state in which an internal operation is being performed, through a status output pin in response to receiving the first command; and generating a selection signal to control a plurality of selectors in an interface circuit to output the status data from each of the plurality of memory devices to the memory controller based on the first command.
US 20180075910 A1 (SEONG) teaching setting the ready/busy line as an output line; and outputting an internal status signal to the ready/busy line set as the output line, wherein the internal status signal indicates whether the semiconductor memory device is performing an operation.
US 20150262630 A1 (SHIRAKAWA) teaching method of notifying availability of data reads by a semiconductor memory device including first and second memory cell arrays and a control circuit, said method comprising: outputting a first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and a second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.
KIM (US 20220199131) teaching system generate a clock signal based on the status signal, wherein the clock control circuit is configured to generate the clock signal set to a relatively low frequency based on the status signal indicating that the memory device is in a busy status, and generate the clock signal set to a relatively high frequency based on the status signal indicating that the memory device is in a ready status.
US 12417034 (KIM) teaching control the memory devices to perform a read operation corresponding to a first descriptor among the plurality of descriptors, perform a first status check operation of checking whether read data read through the read operation is stored in the buffer memory, and determine, based on a result of the first status check operation, read data to be output to an external device from among the read data read through the read operation.
US 11061607 B2 (KOO et al) teaching host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible .
G. Lee et al., "Internal Task-Aware Command Scheduling to Improve Read Performance of Embedded Flash Storage Systems," in IEEE Access, vol. 9, pp. 71638-71650, 2021.
M. Wajid and S. SB, "Architecture for Faster RAM Controller Design with Inbuilt Memory," 2010 2nd International Conference on Computational Intelligence, Communication Systems and Networks, Liverpool, UK, 2010, pp. 147-151.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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