DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2 September 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Duty of Disclosure
Applicant is reminded of 37 C.F.R. 1.56(a-b) which states:
(a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclose information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclose all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by §§ 1.97 (b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:
(1) Prior art cited in search reports of a foreign patent office in a counterpart application, and
(2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.
(b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made of record in the application, and
(1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or
(2) It refutes, or is inconsistent with, a position the applicant takes in:
(i) Opposing an argument of unpatentability relied on by the Office, or
(ii) Asserting an argument of patentability.
(3) A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “226” has been used to designate both a DRAM interface and counter memory cells. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: “command decoder 110” in paragraph 0027 should be --command decoder 106-- and "Bank group 410d” in paragraph 0059 should be --Bank group 410e--. Appropriate correction is required.
Claim Interpretation
The Examiner notes that claims 1, 8, 12, and 16 include the phrase “subset of the memory bank groups”. The broadest reasonable interpretation of the term “subset” includes the empty/null set, a set of any one memory bank group, and the set of all memory bank groups as shown in the following explanation in Hein (Discrete Mathematics): “If A and B are sets and every element of A is also an element of B, then we say that A is a subset of B” (page 13), “every set A is a subset of itself” (page 13), “the empty set is a subset of any set A” (page 13). Based on the examples in the specification, the Examiner wonders whether a strict subset with a plurality of memory bank groups is closer to the intended meaning than simply the term subset.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 7, and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 7, and 14 include the phrase “the second type”, but this phrase lacks antecedent basis in the claims 1 or 12. It is unclear whether this was meant to introduce a second type of refresh command or whether these claims were intended to depend from claims 2 and 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2014/0064008).
In regards to claim 1, Lee teaches an apparatus comprising:
a memory array comprising a plurality of memory bank groups each comprising a plurality of memory banks (“FIG. 4 illustrates that 16 banks BK0 to BK15 exist in the memory device, and four banks is grouped into one group, so that the total of four bank groups BG0 to BG3 are formed.”, paragraph 0032); and
a refresh control circuit configured to perform a refresh operation on a memory bank from a subset of the memory bank groups of the plurality of memory bank groups responsive to a first type of refresh command (“In the second mode, whenever a refresh command is applied to the memory device, one row is refreshed in a half of all bank groups, respectively.”, paragraph 0024).
In regards to claim 2, Lee further teaches that the refresh control circuit is further configured to perform the refresh operation on a memory bank from each of the memory groups of the plurality of memory groups responsive to a second type of command of the first type of refresh command (“In the first mode, whenever a refresh command is applied to the memory device, one row is refreshed in all bank groups, respectively.”, paragraph 0023).
In regards to claim 3, Lee further teaches that the subset of memory bank groups of the plurality of memory bank groups comprises half of the plurality of memory bank groups (“In the second mode, whenever a refresh command is applied to the memory device, one row is refreshed in a half of all bank groups, respectively.”, paragraph 0024).
In regards to claim 5, Lee further teaches that the first type of refresh command is based on a command code (REF 201, figure 2) and a first mode register setting (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033) and the second type of refresh command is based on the command code (REF 101, figure 2) and a second mode register setting (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033).
In regards to claim 6, Lee further teaches the mode register setting is set by a host (“The refresh mode set by the setting circuit 440 is a refresh mode instructed by the memory controller.”, paragraph 0033).
In regards to claim 7, Lee further teaches that an amount of time to perform the refresh operation responsive to the first type of refresh command is longer than the amount of time to perform the refresh operation responsive to the second type of refresh command (“In the second mode, since the half of all bank groups is refreshed in response to a one-time refresh command, a refresh operation period, that is, tRFC may be set to be smaller than that of the first mode.”, paragraph 0024).
In regards to claim 12, Lee teaches a method comprising:
receiving a first type of refresh command (“In the second mode, whenever a refresh command is applied to the memory device, one row is refreshed in a half of all bank groups, respectively.”, paragraph 0024);
performing a refresh operation on a memory bank from a subset of memory bank groups from a plurality of memory bank groups responsive to the first type of refresh command (“In the second mode, whenever a refresh command is applied to the memory device, one row is refreshed in a half of all bank groups, respectively.”, paragraph 0024).
In regards to claim 13, Lee further teaches performing the refresh operation on a memory bank from each of memory groups of the plurality of memory groups responsive to a second type of refresh command (“In the first mode, whenever a refresh command is applied to the memory device, one row is refreshed in all bank groups, respectively.”, paragraph 0023).
In regards to claim 14, Lee further teaches that the first type of refresh command is based on a command code (REF 201, figure 2) and a first mode register setting (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033) and the second type of refresh command is based on the command code (REF 101, figure 2) and a second mode register setting (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033).
Claims 1, 2, 4, 12, 13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. (US 2016/0254044).
In regards to claim 1, Bains teaches an apparatus comprising:
a memory array (memory resources 130, figure 1) comprising a plurality of memory bank groups (bank groups 132, figure 1) each comprising a plurality of memory banks (banks 134, figure 1); and
a refresh control circuit (refresh logic 152, figure 1) configured to perform a refresh operation on a memory bank from a subset of the memory bank groups of the plurality of memory bank groups (“The memory can refresh the identified bank(s) across all bank groups in response to the refresh command, 426.”, paragraph 0056) responsive to a first type of refresh command (“In one embodiment, the memory controller generates a refresh command identifying the bank(s) to refresh, 420.”, paragraph 0056).
In regards to claim 2, Bains further teaches that the refresh control circuit is further configured to perform the refresh operation on a memory bank from each of the memory groups of the plurality of memory groups responsive to a second type of command of the first type of refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047).
In regards to claim 4, Bains further teaches that the refresh control circuit is further configured to perform the refresh operation on all of the memory banks of the plurality of memory banks responsive to a third type of refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047).
In regards to claim 12, Bains teaches a method comprising:
receiving a first type of refresh command (“In one embodiment, the memory controller generates a refresh command identifying the bank(s) to refresh, 420. … In one embodiment, the memory receives and decodes the refresh command, 424.”, paragraph 0056;
performing a refresh operation on a memory bank from a subset of memory bank groups from a plurality of memory bank groups responsive to the first type of refresh command (“The memory can refresh the identified bank(s) across all bank groups in response to the refresh command, 426.”, paragraph 0056).
In regards to claim 13, Bains further teaches performing the refresh operation on a memory bank from each of memory groups of the plurality of memory groups responsive to a second type of refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047).
In regards to claim 15, Bains further teaches receiving a third type of refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047); and
performing a refresh operation on all memory banks from all memory bank groups of the plurality of memory bank groups responsive to the third refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-11 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bains et al. (US 2016/0254044) in view of Lee (US 2014/0064008).
In regards to claim 8, Bains teaches an apparatus comprising:
a memory array (memory resources 130, figure 1) comprising a plurality of memory bank groups (bank groups 132, figure 1) each comprising a plurality of memory banks (banks 134, figure 1);
a refresh state control circuit configured to issue a first, second, and third type of refresh signal (“In one embodiment, the memory receives and decodes the refresh command, 424. The memory can refresh the identified bank(s) across all bank groups in response to the refresh command, 426.”, paragraph 0056); and
a refresh address generator configured to generate a row address to be refreshed in a set of memory banks (“In one embodiment, memory 120 uses counter 126 to keep track of row refreshes. In one embodiment, counter 116 can include bank counters and a global counter.”, paragraph 0032), wherein the set of memory banks is all of the memory banks in all of the memory bank groups of the plurality of memory bank groups responsive to the first refresh signal (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047) and the set of memory banks is a memory bank from a subset of memory bank groups of the plurality of memory bank groups responsive to the third refresh signal (“In one embodiment, the memory controller generates a refresh command identifying the bank(s) to refresh, 420.”, paragraph 0056).
Bains fails to teach that the set of memory banks is a memory bank from each memory bank group of the plurality of memory bank groups responsive to the second refresh signal. Lee teaches that the set of memory banks is a memory bank from each memory bank group of the plurality of memory bank groups responsive to the second refresh signal (“In the first mode, whenever a refresh command is applied to the memory device, one row is refreshed in all bank groups, respectively.”, paragraph 0023) in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bains with Lee such that the set of memory banks is a memory bank from each memory bank group of the plurality of memory bank groups responsive to the second refresh signal in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (id.).
In regards to claim 9, Bains further teaches that the first refresh signal is based on a first refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047) and the second refresh signal and the third refresh signal are based on a second refresh command (“Command 214 illustrates a Refresh per bank, with bit A12 set low.”, paragraph 0047).
In regards to claim 10, Lee further teaches that the second refresh signal and the third refresh signal are further based on a mode register setting (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033).
In regards to claim 11, Bains further teaches that an amount of time to refresh the set of memory banks responsive to the first refresh signal is shorter than the amount of time to refresh the set of memory banks responsive to the second refresh signal and the amount of time to refresh the set of memory banks responsive to the second refresh signal is shorter than the amount of time to refresh the set of memory banks responsive to the third refresh signal (“By issuing a refresh command from the memory controller which the memory devices execute on banks across different bank groups, the memory controller can issue fewer refresh commands in certain conditions. For example, in one embodiment, the memory controller can issue 8 refresh commands where it would have issued 32 instead, referring to issuing 8 per bank refreshes that are applied across 4 bank groups, instead of issuing 32 per bank refreshes to refresh the 8 banks each in each bank group separately.”, paragraph 0051).
In regards to claim 16, Bains teaches an apparatus comprising:
a memory array (memory resources 130, figure 1) comprising a plurality of memory bank groups (bank groups 132, figure 1) each comprising a plurality of memory banks (banks 134, figure 1); and
a refresh control circuit (refresh logic 152, figure 1) configured to:
perform a refresh operation on all memory banks from each of the memory bank groups of the plurality of memory bank groups responsive to a first refresh signal (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047); and
perform a refresh operation on a memory bank from a subset of memory bank groups of the plurality of memory bank groups responsive to a third refresh signal (“The memory can refresh the identified bank(s) across all bank groups in response to the refresh command, 426.”, paragraph 0056).
Bains fails to teach perform a refresh operation on a memory bank from each of the memory bank groups of the plurality of memory bank groups responsive to a second refresh signal. Lee teaches perform a refresh operation on a memory bank from each of the memory bank groups of the plurality of memory bank groups responsive to a second refresh signal (“In the first mode, whenever a refresh command is applied to the memory device, one row is refreshed in all bank groups, respectively.”, paragraph 0023) in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bains with Lee to include perform a refresh operation on a memory bank from each of the memory bank groups of the plurality of memory bank groups responsive to a second refresh signal in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (id.).
In regards to claim 17, Lee further teaches a mode register including a mode register setting, wherein the second refresh signal is based on the mode register setting having a first value and the third refresh signal is based on the mode register setting having a second value (“The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033).
In regards to claim 18, Bains further teaches the refresh control circuit comprises a refresh state control circuit (“In one embodiment, the memory receives and decodes the refresh command, 424. The memory can refresh the identified bank(s) across all bank groups in response to the refresh command, 426.”, paragraph 0056) configured to:
provide the first refresh signal responsive to a first refresh command (“Command 212 illustrates a Refresh all banks command, with bit A12 set high.”, paragraph 0047); and
provide the third refresh signal responsive to the second refresh command (“Command 214 illustrates a Refresh per bank, with bit A12 set low.”, paragraph 0047).
Lee further teaches provide the second refresh signal responsive to a second refresh command and a first mode register setting (“In the first mode, whenever a refresh command is applied to the memory device, one row is refreshed in all bank groups, respectively.”, paragraph 0023; “The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033); and
provide the third refresh signal responsive to the second refresh command and a second mode register setting (“In the second mode, whenever a refresh command is applied to the memory device, one row is refreshed in a half of all bank groups, respectively. “, paragraph 0024; “The setting circuit 440 is configured to set a refresh mode using the addresses ADDS input through the address input unit 420 at the time of activation of the setting command MRS. The refresh mode may include a first mode, a second mode, and a third mode.”, paragraph 0033).
In regards to claim 19, Lee further teaches that the mode register setting is set by a host (“The command input unit 410 is configured to receive commands CMDS applied from the memory controller”, paragraph 0028; “When a combination of the input command signals CMDS corresponds to the setting command MRS, the command decoder 430 activates the setting command MRS”, paragraph 0029).
In regards to claim 20, Bains further teaches that an amount of time to refresh the set of memory banks responsive to the first refresh signal is shorter than the amount of time to refresh the set of memory banks responsive to the second refresh signal and the amount of time to refresh the set of memory banks responsive to the second refresh signal is shorter than the amount of time to refresh the set of memory banks responsive to the third refresh signal (“By issuing a refresh command from the memory controller which the memory devices execute on banks across different bank groups, the memory controller can issue fewer refresh commands in certain conditions. For example, in one embodiment, the memory controller can issue 8 refresh commands where it would have issued 32 instead, referring to issuing 8 per bank refreshes that are applied across 4 bank groups, instead of issuing 32 per bank refreshes to refresh the 8 banks each in each bank group separately.”, paragraph 0051).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7 and 1 of U.S. Patent No. 11,468,938. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the elements in the claims from the present application are also found in the claims of the patent.
In regards to claim 1, claim 7 of U.S. Patent No. 11,468,938 teaches an apparatus comprising (“An apparatus, comprising:”):
a memory array comprising a plurality of memory bank groups each comprising a plurality of memory banks (“a memory array including a first memory bank group and a second memory bank group”); and
a refresh control circuit configured to perform a refresh operation on a memory bank from a subset of the memory bank groups of the plurality of memory bank groups responsive to a first type of refresh command (“logic coupled to a command/address bus and to the memory array, wherein the logic is configured to: perform, in response to a refresh command received via the command/address bus, a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time”).
In regards to claim 12, claim 1 of U.S. Patent No. 11,468,938 teaches a method comprising (“A method comprising:”):
receiving a first type of refresh command (“receiving a refresh command”);
performing a refresh operation on a memory bank from a subset of memory bank groups from a plurality of memory bank groups responsive to the first type of refresh command (“in response to the refresh command: performing a first refresh operation on a first memory bank group of a memory device at a first time, and performing a second refresh operation on a second memory bank group of the memory device at a second time”).
Claims 2, 3, 5-7, 13, and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7 and 1 of U.S. Patent No. 11,468,938 in view of Lee (US 2014/0064008).
Claims 7 and 1 of U.S. Patent No. 11,468,938 teach claims 1 and 12 of the present application. Claims 7 and 1 of U.S. Patent No. 11,468,938 fail to teach the additional limitations of claims 2, 3, 5-7, 13, and 14. Lee teaches the additional limitations of claims 2, 3, 5-7, 13, and 14 as explained above in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claims 7 and 1 of U.S. Patent No. 11,468,938 with Lee to include the additional limitations of claims 2, 3, 5-7, 13, and 14 in order that “a memory device having an insufficient data retention time (a memory device to be processed as fail) becomes available” (id.).
Claims 2, 4, 13, and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7 and 1 of U.S. Patent No. 11,468,938 in view of Bains et al. (US 2016/0254044).
Claims 7 and 1 of U.S. Patent No. 11,468,938 teach claims 1 and 12 of the present application. Claims 7 and 1 of U.S. Patent No. 11,468,938 fail to teach the additional limitations of claims 2, 4, 13, and 15. Bains teaches the additional limitations of claims 2, 4, 13, and 15 as explained above in order to “reduce command bandwidth” (paragraph 0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claims 7 and 1 of U.S. Patent No. 11,468,938 with Bains to include the additional limitations of claims 2, 4, 13, and 15 in order to “reduce command bandwidth” (id.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang (US 2012/0026821) teaches refreshing a select bank group. Lee (US 2014/0068171) teaches adjusting the number of bank groups involved in a refresh. Lee (US 2019/0051347) teaches refreshing even and odd banks. Rehmeyer (US 10,978,132) teaches refreshing a subset of the memory bank groups. Putti (US 2025/0140300) teaches issuing REFpb commands to pairs of banks. Lee (US 2025/0181266) teaches sending refresh commands to a pair of banks.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 21 September 2026
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