DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7, 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12307597 and 10861229. Although the claims at issue are not identical, they are not patentably distinct from each other because each are obvious variants of one another.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11562533. Although the claims at issue are not identical, they are not patentably distinct from each other because each are obvious variants of one another.
Below are the correspondence between the instant application and the patents.
Instant Application
1
2
3
4
5
6
7
8
9
10
12307597
1+2
3
4
5
6
7
8
1
11562533
1
2
3
4
5
6
7
9
8
10
10861229
1+2
3
4
5
6
7
8
1
Instant Application
11
12
13
14
15
16
17
18
19
20
12307597
9+10
11
12
13
14
15+16
17
20
18
19
11562533
11
12
13
14
15
16
17
20
18
19
10861229
9+10
11
12
13
14
15+16
17
20
18
19
Claim 8-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-2, 7 of U.S. Patent No. 12307597 in view of Zhong.
Regarding claim 8, claim1-2, 7 of U.S. Patent No. 12307597 teaches Zhong teaches:
The data block assembly module according to claim 7,
However, U.S. Patent No. 12307597 does not, but Zhong teaches:
wherein the first portion and the second portion are interleaved. (FIG. 4 [0114], “For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.” The interpretation of the “interleaved” are based on the explanation of the spec [0035].)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have combined the teachings of U.S. Patent No. 12307597 with the specific teachings of Zhong to interleaved store the first portion and second portion to improve system efficiency.
Regarding claim 9, claim 1-2, 7 of U.S. Patent No. 12307597 teaches Zhong teaches:
The data block assembly module according to claim 1,
However, U.S. Patent No. 12307597 does not, but Zhong teaches:
wherein: the plurality of vertex parameters comprises attribute data. (FIG. 4, ATTR0, ATTR1)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have combined the teachings of U.S. Patent No. 12307597 with the specific teachings of Zhong to include specific data for the vertex with reasonable expectation of success.
Claim 8-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-2, 7 of U.S. Patent No. 10861229 in view of Zhong.
Regarding claim 8, claim1-2, 7 of U.S. Patent No. 10861229 teaches Zhong teaches:
The data block assembly module according to claim 7,
However, U.S. Patent No. 10861229 does not, but Zhong teaches:
wherein the first portion and the second portion are interleaved. (FIG. 4 [0114], “For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.” The interpretation of the “interleaved” are based on the explanation of the spec [0035].)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have combined the teachings of U.S. Patent No. 10861229 with the specific teachings of Zhong to interleaved store the first portion and second portion to improve system efficiency.
Regarding claim 9, claim 1-2, 7 of U.S. Patent No. 10861229 teaches Zhong teaches:
The data block assembly module according to claim 1,
However, U.S. Patent No. 10861229 does not, but Zhong teaches:
wherein: the plurality of vertex parameters comprises attribute data. (FIG. 4, ATTR0, ATTR1)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have combined the teachings of U.S. Patent No. 10861229 with the specific teachings of Zhong to include specific data for the vertex with reasonable expectation of success.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-12, 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Zhong et al. (US 2016/0350892 A1).
Regarding claim 1, Zhong teaches:
A data block assembly module for processing primitive data in a graphics processing system, ([0031], “A primitive generator on the GPU may receive the attribute information for the vertices of a primitive and generate attribute information for vertices of a corresponding primitive. In this disclosure, the term corresponding primitive refers to the primitive in the second view that includes similar graphics content as the primitive in the first view. It is that the graphics content of the two primitives of the different views are the same that causes the viewer to perceive a 3D volume.” FIG. 4 shows that the primitive data is assembled into primitive blocks. Abstract: “A graphics processing unit (GPU) may combine attribute information for two or more corresponding vertices of corresponding primitives in different views.”) the data block assembly module comprising:
an input configured to receive primitive data that describes each of a first view and a second view; ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67.”) and
a processor arranged to generate a data block, ([0114], “In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67.”) the data block comprising:
vertex data for a plurality of vertices, (FIG. 4: each line is a vertex data. “
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primitive data for a plurality of primitives, wherein the primitive data for a primitive comprises a reference to one or more of the plurality of vertices; ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view.” Above fig. 4 shows A, B, C reference to the vertices.)
wherein the vertex data comprises, for each vertex in the plurality of vertices: (FIG. 4, vertices references A,B, C., FIG. 6, 7 shows more primitives.)
for each of a plurality of vertex parameters, a single vertex parameter value for both the first and second views. (FIG. 4, [0114], “For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views.”)
Regarding claim 2, Zhong teaches:
The data block assembly module according to claim 1, wherein the processor comprises logic configured to store, in a data block, the primitive data for the plurality of primitives, ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67. For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.”) and for each vertex in the plurality of vertices, to store, in the data block, for each of the plurality of vertex parameters, the single vertex parameter value for both the first and second views. (FIG. 4, [0114], “For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views.”)
Regarding claim 4, Zhong teaches:
The data block assembly module according to claim 1, wherein the processor comprises logic configured to determine which vertex parameters are in the plurality of vertex parameters ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67. For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.”) by:
inspecting, for each vertex parameter, code configured to generate a vertex parameter value for the first view and a vertex parameter value for the second view; ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67. For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.”)and
in response to determining that, for a vertex parameter, the code is not capable of generating a vertex parameter value for the first view for any vertex that does not match the vertex parameter for the second view for the same vertex, assigning the vertex parameter to the plurality of vertex parameters. ([0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67. For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views.”)
Regarding claim 5, Zhong teaches:
The data block assembly module according to claim 1, wherein the processor further comprises logic arranged to store control data identifying which vertex parameters are in the plurality of vertex parameters. ( Zhong, [0118]-[0119], “FIG. 5 is text illustrating an example of adding instructions in a vertex shader. As described above, in some examples, compiler 18, graphics driver 14, and/or graphics driver wrapper 16 may be configured to add instructions into vertex shader program 28 to generate modified vertex shader program 30, where modified vertex shader program 30 is configured to process the combined attribute information. For ease, the example of FIG. 5 is described with respect to compiler 18 performing such functions, but may be performed by other modules individually or in combination with compiler 18. Compiler 18 retrieves the source code for vertex shader program 28 from system memory 26. As illustrated by the thick boxes, compiler 18 may add source code to the source code of vertex shader program 28 to include source code for generating position information for a plurality of views (e.g., numViews) and outputting the position information. The result is the source code for modified vertex shader program 30 that is configured to process combined attribute information.”)
Regarding claim 6, Zhong teaches:
The data block assembly module according to claim 1, wherein the data block comprises data for stereoscopic rendering, the input is configured to receive primitive data for the first view and the second view, and the first view is a left view and the second view is a right view. ([0004], “The two images of the stereoscopic view are referred to as a left-eye image and a right-eye image, respectively.” Abstract: “The GPU may process the combined attributed information to generate graphics data for the stereoscopic view.”)
Regarding claim 7, Zhong teaches:
The data block assembly module according to claim 1, wherein the data block (
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a first portion comprising only vertex parameter values for the first view for vertex parameters that are not in the plurality of vertex parameters; (FIG. 4, POS0)
a second portion comprising only vertex parameter values for the second view for vertex parameters that are not in the plurality of vertex parameters; (FIG. 4, POS1) and a third portion comprising only vertex parameter values for the plurality of vertex parameters. (FIG. 4, ATTR0, ATTR1)
Regarding claim 8, Zhong teaches:
The data block assembly module according to claim 7, wherein the first portion and the second portion are interleaved. (FIG. 4 [0114], “For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views. For vertex A, primitive generator 47A may store POS0, which is the position information for vertex A, and POS1, which is the position information for the corresponding vertex in the corresponding primitive of the other view. The same is true for vertex B and C.” The interpretation of the “interleaved” are based on the explanation of the spec [0035].)
Regarding claim 9, Zhong teaches:
The data block assembly module according to claim 1, wherein:the plurality of vertex parameters comprises attribute data. (FIG. 4, ATTR0, ATTR1)
Regarding claim 10, Zhong teaches:
The data block assembly module according to claim 1, wherein the processor is implemented in hardware. (FIG. 3A, GPU 20)
Regarding claim 16, Zhong teaches:
A data structure stored in a memory element for storing primitive data for at least a first view and a second view, ([0088], “Primitive generator 47A or 47B receive attribute information from vertex array 46. Vertex arrays 46 may be a memory unit of system memory 26 configured to store first attribute information for a vertex of a first primitive of a first view (e.g., generated from the execution of application 32).”[0114], “As illustrated in FIG. 4, front-end of primitive generator 47A receives vertices A, B, and C for a primitive of a first view. In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67.”)
wherein the primitive data comprises a plurality of parameters, (FIG. 4: each line is a vertex data. “
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the data structure comprising: vertex data for a plurality of vertices; andprimitive data for a plurality of primitives, wherein the primitive data for a primitive comprises a reference to one or more of the plurality of vertices;wherein the vertex data comprises, for each vertex in the plurality of vertices:for each of a plurality of vertex parameters, a single vertex parameter value for both the first and second views. (According to the MPEP 2111.05, The data structure defined here invoke printed matter doctrine, since it only claims the content of information without functional or structural relationship exits. Since there is no functional relationship exits, the printed matter is not given patentable weight in evaluating novelty or nonobviousness (In re DiStefano, 808 F.3d 845, 117 USPQ2d 1265, 1267-68.)
Claim 17-20 still define the data structure, so still are printed matter.(
17. The data structure according to claim 16, comprising data for stereoscopic rendering and wherein the first view is a left view and the second view is a right view.
18. The data structure according to claim 16, wherein the plurality of vertex parameters comprises attribute data.
19. The data structure according to claim 16, wherein vertex parameters not in the plurality of vertex parameters comprises parameters defining a position of the vertex.
20. The data structure according to claim 19, wherein vertex parameters not in the plurality of vertex parameters further comprises parameters defining reflections.)
Claim 11-12, 14-15 recites similar limitations of claim 1-2, 4-5 respectively, thus are rejected using the same rejection rationale respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhong in view of Deguchi (US 2001/0000963 A1).
Regarding claim 3, Zhong in view of Yang teaches:
The data block assembly module according to claim 1, wherein the processor comprises logic configured to determine which vertex parameters are in the plurality of vertex parameters(logic shown in FIG. 11 and corresponding paragraphs.) by:
in response to determining that, for a vertex parameter and for each vertex, the vertex parameter value for the first view and the vertex parameter for the second view match, assigning the vertex parameter to the plurality of vertex parameters. ([0114], “In this example, the front-end of primitive generator 47A may determine attribute information for a primitive of a second view and store this information as combined attribute information in local memory 67. For instance, for vertex A, primitive generator 47A may store attribute information ATTR0 and ATTR1, which may be the same attribute information for the vertex A of the primitive in the first view and for the corresponding vertices of corresponding primitives in the other views.”)
However, Zhong does not explicitly teach:
Deciding whether two parameters are match or not by comparing, for each vertex and each vertex parameter, a vertex parameter value for the first view and a vertex parameter value for the second view;
Deguchi teaches a method of:
Deciding whether two parameters are match or not by comparing, two parameters (126: “If it is determined in step S34 that the attribute n is not a pattern attribute, then b is set to 1 (step S43 shown in FIG. 19). The vertex coordinate data n of the attribute n is compared with the vertex coordinate data b of the higher order attribute b in the file 41 (step S44), and it is determined whether or not all vertex coordinates match one another (step S45). If there is a vertex whose coordinates do not match those of the corresponding vertex, it is determined whether or not the vertex coordinate data b refers to the final record in the file 41”)
Zhong teaches operations based on whether paramters from two vertex match or not, but does not explicitly teach how to decide whether two parameters match or not. Deguchi teaches a method of deciding whether two parameters match or not by comparing.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have combined the teachings of Deguchi into Zhong to explicitly decide whether a vertex parameter value for the first view and a vertex parameter value for the second view match or not.
Claim 13 recites similar limitations of claim 3, thus are rejected using the same rejection rationale.
Conclusion
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/YANNA WU/Primary Examiner, Art Unit 2615
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