DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 13-16 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4 and 9-11 of U.S. Patent No. 12,327,526. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are merely broader versions of the patented claims.
Below is a comparison between present claim 1 and patented claim 1:
Present claim 1
Patented claim 1
A drive control circuit, comprising:
an input circuit, a first output circuit, and a second output circuit; wherein the first output circuit is electrically connected with the input circuit and a first output end, and is configured to output a first output signal from the first output end under control of the input circuit; the second output circuit is electrically connected with the input circuit and a second output end, or electrically connected with the first output end and the second output end, and is configured to output a second output signal from the second output end under control of the input circuit or the first output end; the first output signal and the second output signal are different in at least one of following: an absolute value of a voltage of an effective level, a time length of an effective level within a time length of one frame.
A drive control circuit, comprising:
an input circuit, a first output circuit, and a second output circuit; wherein the first output circuit is electrically connected with the input circuit and a first output end, and is configured to output a first output signal from the first output end under control of the input circuit; the second output circuit is electrically connected with the input circuit and a second output end, or electrically connected with the first output end and the second output end, and is configured to output a second output signal from the second output end under control of the input circuit or the first output end; the first output signal and the second output signal are different in at least one of following: an absolute value of a voltage of an effective level, a time length of an effective level within a time length of one frame,
and a continuous voltage fluctuation stage after an effective level, wherein the first output signal and the second output signal are of opposite phases, wherein the second output circuit comprises: at least one inverting sub-circuit, the inverting sub-circuit is electrically connected with the first output end, the second output end, a first power supply line, and a second power supply line, and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the first output end; polarities of effective levels of the first power supply signal and the second power supply signal are different, wherein the first output circuit comprises at least one inverting sub-circuit, and the inverting sub-circuit is electrically connected with the input circuit and the first output end, wherein the inverting sub-circuit comprises: a first semiconductor-type transistor and a second semiconductor-type transistor, the first semiconductor-type transistor and the second semiconductor-type transistor are of different transistor types; a first electrode of the first semiconductor-type transistor is electrically connected with the first power supply line, and a first electrode of the second semiconductor-type transistor is electrically connected with the second power supply line; an effective level of the first power supply signal provided by the first power supply line and an effective level for starting the first semiconductor-type transistor are of opposite polarities, and an effective level of the second power supply signal provided by the second power supply line and an effective level for starting the second semiconductor-type transistor are of opposite polarities.
As can be seen above, the main difference between the claims is that patented claim 1 recites more features in the drive control circuit. Therefore, present claim 1 is merely a broader version of patented claim 1, and thus is anticipated by patented claim 1.
Claim 13 is similarity rejected over patented claim 3.
Claim 14 is similarity rejected over patented claim 4.
Claim 15 is similarity rejected over patented claim 9.
Claim 16 is similarity rejected over patented claim 9.
Claim 19 is similarity rejected over patented claim 11.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,327,526 in view of Kim et al. (US 2022/0208075).
Regarding claim 2, patented claim 1 does not specifically disclose the drive control circuit according to claim 1, wherein a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame, wherein an effective level of the first output signal and an effective level of the second output signal are of a same polarity.
However, Kim discloses a drive control circuit (Fig. 5; [0102], e.g., a gate driving circuit GD), comprising:
an input circuit ([0105], e.g., input circuit Q2C), a first output circuit ([0106], e.g., first output circuit PDE and PUE), and a second output circuit ([0110]-[0111], e.g., second output circuit SVL and SVH);
wherein the first output circuit is electrically connected with the input circuit and a first output end (e.g., the first output circuit PDE and PUE is connected with the input circuit Q2C and a first output end EV/EM(n)), and is configured to output a first output signal from the first output end under control of the input circuit ([0106], e.g., output the first output signal EM(n) under control of the input circuit Q2C);
the second output circuit is electrically connected with the input circuit and a second output end, or electrically connected with the first output end and the second output end (e.g., the second output circuit SVL and SVH is connected with the first output end EM(n) and the second output end SV/Scan1(n)), and is configured to output a second output signal from the second output end under control of the input circuit or the first output end ([0110]-[0111], e.g., output a second output signal Scan1(n) under control of the first output end EM(n));
the first output signal and the second output signal are different in at least one of following: an absolute value of a voltage of an effective level, a time length of an effective level within a time length of one frame (Fig. 6; e.g., a time length of an effective level of the first output signal EM(n) within a time length of one frame is greater than a time length of an effective level of the second output signal Scan1(n) within a time length of one frame),
wherein a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame, and an effective level of the first output signal and an effective level of the second output signal are of a same polarity (Fig. 6; e.g., an effective level of the first output signal EM(n) and an effective level of the second output signal Scan1(n) are of a same polarity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Kim in the invention as taught by patented claim 1 for providing a first output signal and a second output signal such that a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame and an effective level of the first output signal and an effective level of the second output signal are of a same polarity so that a gate electrode of a driving transistor of a pixel circuit can be initialized and a threshold voltage thereof can be sampled during a refresh frame (see [0133] of Kim).
Claims 3, 5-6, 8 and 11-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,327,526 in view of Yamamoto (US 2022/0392403).
Regarding claim 3, patented claim 1 does not specifically disclose the drive control circuit according to claim 1, wherein the input circuit is electrically connected with at least one output control node and configured to control a potential of the output control node; the first output circuit is electrically connected with the at least one output control node and the first output end, and is configured to control the first output end to output the first output signal under control of the at least one output control node; the second output circuit is electrically connected with one output control node and the second output end, and is configured to control the second output end to output the second output signal under control of the output control node.
However, Yamamoto discloses a drive control circuit (Figs 1 and 5; [0167], e.g., a drive control circuit 3), comprising:
an input circuit (e.g., input circuit 311), a first output circuit ([0169], e.g., a first output circuit 322), and a second output circuit ([0169], e.g., a second output circuit 321);
wherein the first output circuit is electrically connected with the input circuit and a first output end (e.g., the first output circuit 322 is connected with the input circuit 311 and the first output end OUT2), and is configured to output a first output signal from the first output end under control of the input circuit ([0169], e.g., output the first output signal OUT2 under control of the input circuit 311);
the second output circuit is electrically connected with the input circuit and a second output end (e.g., the second output circuit 321 is connected with the input circuit 311 and the second output end OUT1), and is configured to output a second output signal from the second output end under control of the input circuit ([0169], e.g., output the second output signal OUT1 under control of the input circuit 311);
the first output signal and the second output signal are different in a time length of an effective level within a time length of one frame (Fig. 7; [0175]-[0180, e.g., a time length of an effective level of the first output signal OUT2 and a time length of an effective level of the second output signal OUT1 are different within a time length of a frame),
wherein the input circuit is electrically connected with at least one output control node and configured to control a potential of the output control node (Fig. 1; [0169], e.g., the input circuit 311 controls a potential of the output control node N1);
the first output circuit is electrically connected with the at least one output control node and the first output end (e.g., the first output circuit 322 is connected with the output control node N1 and the first output end OUT2), and is configured to control the first output end to output the first output signal under control of the at least one output control node (Fig. 7; [0177], e.g., the first output signal OUT2 is output under control of the output control node N1/N2);
the second output circuit is electrically connected with one output control node and the second output end (e.g., the second output circuit 321 is connected with the output control node N1 and the second output end OUT1), and is configured to control the second output end to output the second output signal under control of the output control node (Fig. 7; [0175], e.g., the first output signal OUT2 is output under control of the output control node N1/N2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Yamamoto in the invention as taught by patented claim 1 for electrically connecting an input circuit with at least one output control node so that a first output circuit and a second output circuit can output scanning signals to drive a pixel circuit in a display device while suppressing an increase in processing cost (see [0114] of Yamamoto).
Regarding claim 5, Yamamoto further discloses the drive control circuit, wherein the second output circuit comprises: an inverting sub-circuit (Fig. 1, e.g., the second output circuit 321 comprises an inverting circuit), and the inverting sub-circuit is electrically connected with the output control node (e.g., the output control node N1), the second output end (e.g., the output end OUT1), a first power supply line (e.g., VGH), and a second power supply line (e.g., VGL), and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the output control node (Fig. 7; [0175]); polarities of effective levels of the first power supply signal and the second power supply signal are different (e.g., the polarities of VGH and the VGL are different), and an absolute value of a voltage of an effective level of the first power supply signal is greater than or equal to an absolute value of a voltage of an effective level of the second power supply signal (Fig. 6; e.g., the absolute value of the VGH is greater than or equal to the absolute value of the VGL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention as taught by patented claim 1 in view of Yamamoto for comprising an inverting sub-circuit electrically connected with an output control node, a second output end, a first power supply line and a second power supply line in order to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the output control node.
Regarding claim 6, Yamamoto discloses a drive control circuit (Fig. 18; [0227]-[0240]), wherein an input circuit comprises:
an input sub-circuit (e.g., input sub-circuit 311) and a control sub-circuit (e.g., control sub-circuit 312);
the input sub-circuit (e.g., 311) is electrically connected with a signal input end (e.g., signal input end S), a first clock end (e.g., CK1), and a first control node (e.g., N1), and is configured to control a potential of the first control node under control of the signal input end and the first clock end;
the control sub-circuit (e.g., 312) is at least electrically connected with the first control node (e.g., N1), a first power supply line (e.g., VGH), a second power supply line (e.g., VGL), a first output control node (e.g., the transistor M8 is connected to a first output control node which is electrically connected with the first control node N1), and a second output control node (e.g., N2), and is configured to control potentials of the first output control node and the second output control node under control of the first control node ([0232]);
a first output circuit (e.g., 322) is electrically connected with the first output control node (e.g., the first output control node is electrically connected with the first control node N1), the second output control node (e.g., N2), and the first output end (e.g., OUT2), and is configured to control the first output end to output the first output signal under control of the first output control node and the second output control node (see Fig.19 and [0234]);
a second output circuit (e.g., 321) is electrically connected with the first control node (e.g., N1) and is configured to control the second output end to output the second output signal under control of the first control node (Fig. 19 and [0232], e.g., output the second output signal OUT1 under the control of the first control node N1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Yamamoto in the invention as taught by patented claim 1 for comprising an input sub-circuit configured to control a potential of a first control node under control of a signal input end and a first clock end and a control sub-circuit configured to control potentials of a first output control node and a second output control node under control of the first control node so that a first output circuit and a second output circuit can output scanning signals to drive a pixel circuit in a display device while suppressing an increase in processing cost (see [0114] of Yamamoto).
Regarding claim 8, Yamamoto further discloses the drive control circuit, wherein the second output circuit comprises:
an inverting sub-circuit (Fig. 18; e.g., the second output circuit 321 comprises an inverting sub-circuit M4 and M5), and the inverting sub-circuit is electrically connected with the first control node (e.g., N1), the second output end (e.g., OUT1), the first power supply line (e.g., VGH), and the second power supply line (e.g., VGL), and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the first control node (Fig. 19; e.g., output a first power supply signal VGH or a second power supply signal VGL under the control of the first control node N1);
polarities of effective levels of the first power supply signal and the second power supply signal are different (e.g., the polarities of the effective level of VGH and VGL are different), and an absolute value of a voltage of an effective level of the first power supply signal is greater than or equal to an absolute value of a voltage of an effective level of the second power supply signal (Fig. 6; e.g., absolute value of VGH is greater than or equal to an absolute value of VGL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention as taught by patented claim 1 in view of Yamamoto for comprising an inverting sub-circuit electrically connected with a first control node, a second output end, a first power supply line and a second power supply line in order to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the first control node.
Regarding claim 11, patented claim 1 discloses wherein an inverting sub-circuit comprises: a first semiconductor-type transistor and a second semiconductor-type transistor, the first semiconductor-type transistor and the second semiconductor-type transistor are of different transistor types. Yamamoto further discloses wherein the inverting sub-circuit (e.g., the inverting sub-circuit 321) comprises:
a first type transistor and a second type transistor, the first type transistor and the second type transistor are of different transistor types (e.g., P-type transistor M4 and N-type transistor M5);
a first electrode of the first type transistor is electrically connected with the first power supply line (e.g., a first electrode of the P-type transistor M4 is connected with the VGH), and a first electrode of the second type transistor is electrically connected with the second power supply line (e.g., a first electrode of the N-type transistor M5 is connected with the VGL);
an effective level of the first power supply signal provided by the first power supply line and an effective level for starting the first type transistor are of opposite polarities (e.g., an effective level of the first power supply signal VGH and an effective level VGL for turning on M4 are of opposite polarities), and an effective level of the second power supply signal provided by the second power supply line and an effective level for starting the second semiconductor-type transistor are of opposite polarities (e.g., an effective level of the second power supply signal VGL and an effective level VGH for turning on M5 are of opposite polarities).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention as taught by patented claim 1 in view of Yamamoto for providing a first semiconductor type transistor and a second semiconductor type transistor in the inverting sub-circuit in order to achieve a reduction in power consumption (see [0008] of Yamamoto).
Regarding claim 12, Yamamoto further discloses wherein the first output circuit (Fig. 1; e.g., the first output circuit 322) at least comprises:
a third output transistor and a fourth output transistor (e.g., third transistor M2 and fourth transistor M1); the third output transistor and the fourth output transistor are of a same transistor type (e.g., P-type transistors);
a control electrode of the third output transistor is electrically connected with a first output control node (e.g., a gate electrode of M2 is connected with a first output control node), a first electrode of the third output transistor is electrically connected with a first power supply line (e.g., VGH), and a second electrode of the third output transistor is electrically connected with the first output end (e.g., OUT2);
a control electrode of the fourth output transistor is electrically connected with a second output control node (e.g., a gate electrode of M1 is connected with a second output control node), a first electrode of the fourth output transistor is electrically connected with a second power supply line or a second clock end (e.g., CK2), and a second electrode of the fourth output transistor is electrically connected with the first output end (e.g., OUT2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention as taught by patented claim 1 in view of Yamamoto for electrically connecting a P-type third transistor with a first output control node, a first power supply line and a first output end and electrically connecting a P-type fourth transistor with a second output control node, a second clock end and the first output end in order to output a first output signal under control of the first output control node and the second output control node.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation “the input power supply”. There is insufficient antecedent basis for this limitation in the claim.
Claims 17 and 18 recite the limitation “the second power supply line”. There is insufficient antecedent basis for this limitation in the claims. Claim 16 recites two second power supply lines, therefore it is unclear if the second power supply line in claims 17 and 18 corresponds to the first second power supply line or the second second power supply line mentioned in claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 8, and 12-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yamamoto (US 2022/0392403).
Regarding claim 1, Yamamoto discloses a drive control circuit (Figs 1 and 5; [0167], e.g., a drive control circuit 3), comprising:
an input circuit (e.g., input circuit 311), a first output circuit ([0169], e.g., a first output circuit 322), and a second output circuit ([0169], e.g., a second output circuit 321);
wherein the first output circuit is electrically connected with the input circuit and a first output end (e.g., the first output circuit 322 is connected with the input circuit 311 and the first output end OUT2), and is configured to output a first output signal from the first output end under control of the input circuit ([0169], e.g., output the first output signal OUT2 under control of the input circuit 311);
the second output circuit is electrically connected with the input circuit and a second output end, or electrically connected with the first output end and the second output end (e.g., the second output circuit 321 is connected with the input circuit 311 and the second output end OUT1), and is configured to output a second output signal from the second output end under control of the input circuit or the first output end ([0169], e.g., output the second output signal OUT1 under control of the input circuit 311);
the first output signal and the second output signal are different in at least one of following: an absolute value of a voltage of an effective level, a time length of an effective level within a time length of one frame (Fig. 7; [0175]-[0180, e.g., a time length of an effective level of the first output signal OUT2 and a time length of an effective level of the second output signal OUT1 are different within a time length of a frame).
Regarding claim 3, Yamamoto further discloses the drive control circuit according to claim 1, wherein the input circuit is electrically connected with at least one output control node and configured to control a potential of the output control node (Fig. 1; [0169], e.g., the input circuit 311 controls a potential of the output control node N1);
the first output circuit is electrically connected with the at least one output control node and the first output end (e.g., the first output circuit 322 is connected with the output control node N1 and the first output end OUT2), and is configured to control the first output end to output the first output signal under control of the at least one output control node (Fig. 7; [0177], e.g., the first output signal OUT2 is output under control of the output control node N1/N2);
the second output circuit is electrically connected with one output control node and the second output end (e.g., the second output circuit 321 is connected with the output control node N1 and the second output end OUT1), and is configured to control the second output end to output the second output signal under control of the output control node (Fig. 7; [0175], e.g., the first output signal OUT2 is output under control of the output control node N1/N2).
Regarding claim 5, Yamamoto further discloses the drive control circuit according to claim 3, wherein the second output circuit comprises: an inverting sub-circuit (Fig. 1, e.g., the second output circuit 321 comprises an inverting circuit), and the inverting sub-circuit is electrically connected with the output control node (e.g., the output control node N1), the second output end (e.g., the output end OUT1), a first power supply line (e.g., VGH), and a second power supply line (e.g., VGL), and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the output control node (Fig. 7; [0175]); polarities of effective levels of the first power supply signal and the second power supply signal are different (e.g., the polarities of VGH and the VGL are different), and an absolute value of a voltage of an effective level of the first power supply signal is greater than or equal to an absolute value of a voltage of an effective level of the second power supply signal (Fig. 6; e.g., the absolute value of the VGH is greater than or equal to the absolute value of the VGL).
Regarding claim 6, Yamamoto further discloses the drive control circuit (Fig. 18; [0227]-[0240]) according to claim 1, wherein the input circuit comprises:
an input sub-circuit (e.g., input sub-circuit 311) and a control sub-circuit (e.g., control sub-circuit 312);
the input sub-circuit (e.g., 311) is electrically connected with a signal input end (e.g., signal input end S), a first clock end (e.g., CK1), and a first control node (e.g., N1), and is configured to control a potential of the first control node under control of the signal input end and the first clock end;
the control sub-circuit (e.g., 312) is at least electrically connected with the first control node (e.g., N1), a first power supply line (e.g., VGH), a second power supply line (e.g., VGL), a first output control node (e.g., the transistor M8 is connected to a first output control node which is electrically connected with the first control node N1), and a second output control node (e.g., N2), and is configured to control potentials of the first output control node and the second output control node under control of the first control node ([0232]);
the first output circuit is electrically connected with the first output control node (e.g., the OUT1), the second output control node (e.g., N2), and the first output end (e.g., OUT2), and is configured to control the first output end to output the first output signal under control of the first output control node and the second output control node (see Fig.19 and [0234]);
the second output circuit is electrically connected with the first control node (e.g., N1) and is configured to control the second output end to output the second output signal under control of the first control node (Fig. 19 and [0232], e.g., output the second output signal OUT1 under the control of the first control node N1).
Regarding claim 8, Yamamoto further discloses the drive control circuit according to claim 6, wherein the second output circuit comprises:
an inverting sub-circuit (Fig. 18; e.g., the second output circuit 321 comprises an inverting sub-circuit M4 and M5), and the inverting sub-circuit is electrically connected with the first control node (e.g., N1), the second output end (e.g., OUT1), the first power supply line (e.g., VGH), and the second power supply line (e.g., VGL), and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under control of the first control node (Fig. 19; e.g., output a first power supply signal VGH or a second power supply signal VGL under the control of the first control node N1);
polarities of effective levels of the first power supply signal and the second power supply signal are different (e.g., the polarities of the effective level of VGH and VGL are different), and an absolute value of a voltage of an effective level of the first power supply signal is greater than or equal to an absolute value of a voltage of an effective level of the second power supply signal (Fig. 6; e.g., absolute value of VGH is greater than or equal to an absolute value of VGL).
Regarding claim 12, Yamamoto further discloses the drive control circuit according to claim 3, wherein the first output circuit (Fig. 1; e.g., the first output circuit 322) at least comprises:
a third output transistor and a fourth output transistor (e.g., third transistor M2 and fourth transistor M1); the third output transistor and the fourth output transistor are of a same transistor type (e.g., P-type transistors);
a control electrode of the third output transistor is electrically connected with a first output control node (e.g., a gate electrode of M2 is connected with a first output control node), a first electrode of the third output transistor is electrically connected with a first power supply line (e.g., VGH), and a second electrode of the third output transistor is electrically connected with the first output end (e.g., OUT2);
a control electrode of the fourth output transistor is electrically connected with a second output control node (e.g., a gate electrode of M1 is connected with a second output control node), a first electrode of the fourth output transistor is electrically connected with a second power supply line or a second clock end (e.g., CK2), and a second electrode of the fourth output transistor is electrically connected with the first output end (e.g., OUT2).
Regarding claim 13, Yamamoto further discloses a gate driver circuit (Figs 4-5; [0161], e.g., a gate driver 300), comprising a plurality of cascaded drive control circuits ([0162], e.g., five cascaded drive control circuits) according to claim 1; wherein a signal input end of a first stage drive control circuit is electrically connected with a start signal line (e.g., the gate start pulse signal is a signal provide as a set signal S to the unit circuit 3(1) of the first stage), and a signal input end of an (i+1)-th stage drive control circuit is electrically connected with a first output end of an i-th stage drive control circuit, wherein i is an integer greater than 0 (see Fig. 5 and [0162]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2022/0392403) in view of Kim et al. (US 2022/0208075).
Regarding claim 2, Yamamoto does not specifically disclose the drive control circuit according to claim 1, wherein a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame, wherein an effective level of the first output signal and an effective level of the second output signal are of a same polarity.
However, Kim discloses a drive control circuit (Fig. 5; [0102], e.g., a gate driving circuit GD), comprising:
an input circuit ([0105], e.g., input circuit Q2C), a first output circuit ([0106], e.g., first output circuit PDE and PUE), and a second output circuit ([0110]-[0111], e.g., second output circuit SVL and SVH);
wherein the first output circuit is electrically connected with the input circuit and a first output end (e.g., the first output circuit PDE and PUE is connected with the input circuit Q2C and a first output end EV/EM(n)), and is configured to output a first output signal from the first output end under control of the input circuit ([0106], e.g., output the first output signal EM(n) under control of the input circuit Q2C);
the second output circuit is electrically connected with the input circuit and a second output end, or electrically connected with the first output end and the second output end (e.g., the second output circuit SVL and SVH is connected with the first output end EM(n) and the second output end SV/Scan1(n)), and is configured to output a second output signal from the second output end under control of the input circuit or the first output end ([0110]-[0111], e.g., output a second output signal Scan1(n) under control of the first output end EM(n));
the first output signal and the second output signal are different in at least one of following: an absolute value of a voltage of an effective level, a time length of an effective level within a time length of one frame (Fig. 6; e.g., a time length of an effective levelof the first output signal EM(n) within a time length of one frame is greater than a time length of an effective level of the second output signal Scan1(n) within a time length of one frame),
wherein a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame, and an effective level of the first output signal and an effective level of the second output signal are of a same polarity (Fig. 6; e.g., an effective level of the first output signal EM(n) and an effective level of the second output signal Scan1(n) are of a same polarity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Kim in the invention of Yamamoto for providing a first output signal and a second output signal such that a time length of an effective level of the first output signal within a time length of one frame is greater than a time length of an effective level of the second output signal within a time length of one frame and an effective level of the first output signal and an effective level of the second output signal are of a same polarity because the drive control circuit can provide a gate drive signal using an emission signal generating circuit (see [0103]-[0104] of Kim).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2022/0392403).
Regarding claim 11, Yamamoto further discloses the drive control circuit according to claim 5, wherein the inverting sub-circuit (e.g., the inverting sub-circuit 321) comprises:
a first type transistor and a second type transistor, the first type transistor and the second type transistor are of different transistor types (e.g., P-type transistor M4 and N-type transistor M5);
a first electrode of the first type transistor is electrically connected with the first power supply line (e.g., a first electrode of the P-type transistor M4 is connected with the VGH), and a first electrode of the second type transistor is electrically connected with the second power supply line (e.g., a first electrode of the N-type transistor M5 is connected with the VGL);
an effective level of the first power supply signal provided by the first power supply line and an effective level for starting the first type transistor are of opposite polarities (e.g., an effective level of the first power supply signal VGH and an effective level VGL for turning on M4 are of opposite polarities), and an effective level of the second power supply signal provided by the second power supply line and an effective level for starting the second semiconductor-type transistor are of opposite polarities (e.g., an effective level of the second power supply signal VGL and an effective level VGH for turning on M5 are of opposite polarities).
Yamamoto further discloses a transistor can be an oxide semiconductor transistor ([0008], [0022], [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Yamamoto for providing a first semiconductor type transistor and a second semiconductor type transistor by using an oxide semiconductor as a material of a channel layer in a P-type transistor and a N-type transistor in order to achieve a reduction in power consumption (see [0008] of Yamamoto).
Claim(s) 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over WU et al. (US 2021/0097938) in view of Zhang et al. (US 2018/0350306).
Regarding claim 14, WU discloses a display substrate (Fig 7; [0067], e.g., an array substrate 700), comprising:
a display region and a non-display region located at a periphery of the display region (Figs 1 and 7; [0033], e.g., a display region comprises a pixel driving circuit 130 and a non-display region comprises a shift register unit 110 and an inverter 120), wherein the non-display region is provided with a gate driver circuit ([0033]-[0035], e.g., a gate driver circuit comprising the shift register unit 110 and the inverter 120 is provided in the non-display region), the gate driver circuit comprises a plurality of cascaded drive control circuits (Fig. 7; e.g., a plurality of cascaded drive control circuits), a drive control circuit (Fig. 4; [0041]) comprises:
an input circuit (Fig.4; e.g., 210), a first output circuit ([0044]-[0045], e.g., a first output circuit 240 and 250), and a second output circuit ([0048], e.g., the inverter 120);
the first output circuit is electrically connected with the input circuit (Fig. 4; e.g., the first output circuit 240 and 250 connected with the input circuit 210), and the second output circuit is electrically connected with the input circuit or the first output circuit (e.g., the inverter 120 is connected with the first output circuit 240 and 250);
in a first direction, the first output circuit ais located between the input circuit and the second output circuit (Figs 1-2 and 7; e.g., in the row direction, the first output circuit 240 and 250 is located between the input circuit 210 and the inverter 120);
WU does not specifically disclose wherein in the first direction, the input circuit is located between the first output circuit and the second output circuit, or, the second output circuit is located between the input circuit and the first output circuit.
However, Zhang discloses a display substrate, comprising:
a gate driver (Fig. 15; [0083], e.g., the gate drive circuit is integrated on the array substrate of a display panel), wherein the gate driver circuit comprises a plurality of cascaded drive control circuits (Fig. 7; [0059]), a drive control circuit (Fig. 3; [0033]-[0034]) comprises:
an input circuit ([0035], e.g., input circuit 311), a first output circuit ([0035], e.g., a first output circuit 312, 313), and a second output circuit ([0036], e.g., the second output circuit 32);
the first output circuit is electrically connected with the input circuit (Fig. 3; e.g., the first output circuit 312 and 313 connected with the input circuit 311), and the second output circuit is electrically connected with the input circuit or the first output circuit (e.g., the second output circuit 32 is connected with the input circuit 311).
in a first direction, the input circuit is located between the first output circuit and the second output circuit, or, the second output circuit is located between the input circuit and the first output circuit (e.g., the input circuit 311 is located between the first output circuit 312 and 313 and the second output circuit 32 in a row direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhang in the invention of WU for providing a gate driver having an input circuit located between a first output circuit and a second output circuit in a first direction because the gate driver as taught by Zhang have the advantages of simple structure, good driving capability and wide application (see [0084] of Zhang).
Regarding claim 19, WU in view of Zhang further discloses a display apparatus, comprising the display substrate according to claim 14 (WU, [0005], e.g., a display device).
Allowable Subject Matter
Claims 4, 7 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2012/0062525) and Shi et al. (US 2021/0150989) are cited to teach a drive control circuit, comprising: an input circuit, a first output circuit, and a second output circuit; wherein the first output circuit is electrically connected with the input circuit and a first output end, and is configured to output a first output signal from the first output end under control of the input circuit; the second output circuit is electrically connected with the input circuit and a second output end, and is configured to output a second output signal from the second output end under control of the input circuit; the first output signal and the second output signal are different in a time length of an effective level within a time length of one frame.
Han et al. (US 2020/0342808) teaches a drive control circuit, comprising: an input circuit, a first output circuit, and a second output circuit; wherein the first output circuit is electrically connected with the input circuit and a first output end, and is configured to output a first output signal from the first output end under control of the input circuit; the second output circuit is electrically connected with the first output end and the second output end, and is configured to output a second output signal from the second output end under control of the first output end.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HONG ZHOU whose telephone number is (571)270-5372. The examiner can normally be reached 9:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C LEE can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HONG ZHOU/Primary Examiner, Art Unit 2629