DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10 and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim (US 2024/0194138).
Regarding claim 1, Kim discloses a display driving unit (Figs 1-2; [0064], [0079], e.g., the data driver 110 and the gate drivers 121L to 122R) comprising:
a first gate driving buffer configured to supply a first gate signal to a gate line of a display panel (Figs 8 and 10; [0085]-[0087], [0096], [0129], [0141], e.g., a left gate driving buffer configured to supply a first gate signal Eout to a gate line GL of a display panel);
a second gate driving buffer configured to supply a second gate signal to the gate line (e.g., a right gate driving buffer configured to supply a second gate signal Eout to the gate line GL);
a first comparison circuit ([0023], [0065], [0096], [0113], e.g., the timing controller TCON compares each of the first feedback signal FB1 and the second feedback signal FB2 with a normal pattern to individually determine whether the left gate driving buffer 122L and the right gate driving buffer 122R are operating normally) configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the second gate driving buffer ([0096]-[0097], e.g., generating a signal to stop an output of the abnormal left gate driving buffer); and
a second comparison circuit ([0023], [0065], [0096], [0113], [0138], e.g., the timing controller TCON compares each of the first feedback signal FB1 and the second feedback signal FB2 with a normal pattern to individually determine whether the left gate driving buffer 122L and the right gate driving buffer 122R are operating normally) configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the first gate driving buffer ([0096]-[0097], e.g., generating a signal to stop an output of the abnormal right gate driving buffer).
Regarding claim 10, Kim discloses a method of driving a display (Fig. 1; [0064]-[0065], e.g., driving a display 100), the method comprising:
supplying a gate signal to a gate line of a display panel through at least one of a first gate driving buffer and a second gate driving buffer (Figs 8 and 10; [0085]-[0087], [0096], [0129], [0141], e.g., supply a gate signal Eout to a gate line GL through one of a left gate driving buffer and a right gate driving buffer);
generating a first signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the second gate driving buffer supplied to the gate line, through a first comparison circuit ([0023], [0065], [0096]-[0097], [0113], [0138], e.g., generating a signal to stop an output of the abnormal left gate driving buffer by comparing a feedback signal FL1 with previously stored normal feedback pattern by a timing controller); and
generating a second signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the first gate driving buffer supplied to the gate line, through a second comparison circuit (e.g., generating a signal to stop an output of the abnormal right gate driving buffer by comparing a feedback signal FL2 with previously stored normal feedback pattern by the timing controller).
Regarding claim 12, Kim discloses a display device (Fig. 1; [0064]) comprising:
a display panel comprising a pixel array including pixels (e.g., a display panel 100 comprises a pixel array), and a gate line for providing a voltage to a row of the pixels ([0065], e.g., a gate line 103 for providing a voltage to a row of the pixels);
a first gate driving buffer configured to supply a first gate signal to the gate line of the display panel (Figs 8 and 10; [0085]-[0087], [0096], [0129], [0141], e.g., a left gate driving buffer configured to supply a first gate signal Eout to a gate line of a display panel);
a second gate driving buffer configured to supply a second gate signal to the gate line (e.g., a right gate driving buffer configured to supply a second gate signal to the gate line);
a first comparison circuit ([0023], [0065], [0096], [0113], [0138], e.g., the timing controller TCON compares each of the first feedback signal FB1 and the second feedback signal FB2 with a normal pattern to individually determine whether the left gate driving buffer 122L and the right gate driving buffer are operating normally) configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the second gate driving buffer ([0096]-[0097], e.g., generating a signal to stop an output of the abnormal left gate driving buffer); and
a second comparison circuit ([0138], e.g., the timing controller TCON compares each of the first feedback signal FB1 and the second feedback signal FB2 with a normal pattern to individually determine whether the left gate driving buffer 122L and the right gate driving buffer are operating normally) configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the first gate driving buffer ([0096]-[0097], e.g., generating a signal to stop an output of the abnormal right gate driving buffer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 9, 13-14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0194138) in view of PYUN et al. (US 2018/0315369).
Regarding claim 2, Kim further discloses the display driving unit of claim 1, wherein the first gate driving buffer comprises: first gate driving logic (Figs 7-8; [0125], e.g., left shift register ST(1)) configured to output a driving signal for activating the gate line; and the second gate driving buffer comprises: second gate driving logic configured to output a driving signal for activating the gate line (Figs 7-8; [0125], e.g., right shift register ST(1))
Kim does not specifically disclose wherein the first gate driving buffer comprises: a first level shifter configured to increase a level of an output signal of the first gate driving logic, and the second gate driving buffer comprises: a second level shifter configured to increase a level of an output signal of the second gate driving logic.
However, PYUN discloses a display driving unit (Fig. 1; [0050]) wherein a first gate driving buffer (Fig. 6; [0098], e.g., 314a) comprises:
first gate driving logic (Figs 6 and 8; [0116], e.g., shift register 315) configured to output a driving signal for activating a gate line ([0118], e.g., GS); and a first level shifter configured to increase a level of an output signal of the first gate driving logic (e.g., the level shifter 316), and a second gate driving buffer (e.g., 310b) comprises: second gate driving logic (e.g., shift register 315) configured to output a driving signal for activating the gate line; and a second level shifter configured to increase a level of an output signal of the second gate driving logic (e.g., the level shifter 316).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of PYUN in the invention of Kim for providing a level shifter in order to amplify a level of a gate signal based on a gate-on voltage and a gate-off voltage (see [0118] of PYUN).
Regarding claim 3, Kim in view of PYUN further discloses the display driving unit of claim 2, wherein the first gate driving buffer further comprises a first switch for coupling the first level shifter to a first end of the gate line (Fig. 8 of Kim, [0129], e.g., a first output puffer BUF for coupling the first level shifter to a first end of the gate line. Also see Fig. 8 and [0118] of PYUN), and the second gate driving buffer further comprises a second switch for coupling the second level shifter to a second end of the gate line (Fig. 8 of Kim, [0129], e.g., a second output puffer BUF for coupling the second level shifter to a second end of the gate line. Also see Fig. 8 and [0118] of PYUN).
Regarding claim 9, Kim further discloses the display driving unit of claim 3, further comprising: a controller configured to control at least one of the first switch and the second switch based on at least one of an output signal of the first comparison circuit and an output signal of the second comparison circuit (Figs 12-14 and [0158]-[0159], e.g., disable the first output buffer by direct-currentizing the gate timing control signals that control the clocks ECLK1 and ECLK2 transmitted to the second EM driver GIP(R) and inputting the DC voltage of the gate-off voltage VGH to the EM driver GIP(R)).
Regarding claim 13, this claim is rejected under the same rationale as claim 2.
Regarding claim 14, this claim is rejected under the same rationale as claim 3.
Regarding claim 19, this claim is rejected under the same rationale as claim 9.
Claim(s) 4-5, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0194138) in view of PYUN et al. (US 2018/0315369), and further in view of Kim et al. (US 2007/0079192, hereinafter referred to as Kim192).
Regarding claim 4, Kim in view of PYUN does not specifically disclose the display driving unit of claim 2, further comprising: a first internal buffer configured to decrease a level of the output signal of the second gate driving buffer; and a second internal buffer configured to decrease a level of the output signal of the first gate driving buffer.
However, Kim192 discloses a gate driver (Fig 2; [0042], e.g., 200) comprising: an internal buffer configured to decrease a level of an output signal (Fig. 3; [0077]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Kim192 in the invention of Kim in view of PYUN for providing a first internal buffer for decreasing a level of an output signal of a second gate driving buffer and a second internal buffer configured to decrease a level of an output signal of a first gate driving buffer in order to decrease output signals to a sufficient voltage level to turn on/off transistors of a pixel portion.
Regarding claim 5, Kim in view of PYUN and Kim192 further discloses the display driving unit of claim 4, wherein each of the first internal buffer and the second internal buffer comprises at least one inverter connected in series (Kim192, Fig. 5; [0077]).
Regarding claim 15, this claim is rejected under the same rationale as claim 4.
Regarding claim 20, this claim is rejected under the same rationale as claim 5.
Allowable Subject Matter
Claim 21 is allowed.
Claims 6-8, 11 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 6 and 16 the primary reason for indicating allowable subject matter is that the claims recite “wherein the first comparison circuit is configured to compare the output signal of the first gate driving logic and an output signal of the first internal buffer while the gate line is activated by the second gate driving buffer” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Regarding claims 7 and 17 the primary reason for indicating allowable subject matter is that the claims recite “wherein the second comparison circuit is configured to compare the output signal of the second gate driving logic and an output signal of the second internal buffer while the gate line is activated by the first gate driving buffer” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Regarding claim 11, the primary reasons for indicating allowable subject matter is that the claim recites “wherein the generating of the first signal comprises, while the gate line is activated by the second gate driving buffer: generating a level adjusted signal by adjusting a level of the output signal of the second gate driving buffer; and comparing the level adjusted signal and an output signal of a gate driving logic of the first gate driving buffer” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Regarding claim 21, the primary reason for indicating allowable subject matter is that the claim recites “a first comparison circuit configured to supply a first signal to the controller when a comparison of a first output signal of the second gate driving buffer and a first reference signal from the first gate driving buffer indicates the second gate driving buffer is in an abnormal state; and a second comparison circuit configured to supply a second signal to the controller when a comparison of a second output signal of the first gate driving buffer and a second reference signal from the second gate driving buffer indicates the first gate driving buffer is in the abnormal state” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cao (US 2017/0256216) discloses a GOA drive system comprising two GOA modules respectively provided at two sides of a liquid crystal display area wherein each GOA module is electrically coupled to one automatic detection interrupting function module correspondingly, and each automatic detection interrupting function module receives a feedback signal transmitted from the GOA unit circuit of the last stage of the GOA module, and by detecting whether the feedback signal is normal or abnormal.
Saito (US 2019/0362661) discloses a display device comprising: a first gate driver IC having a plurality of first terminals connected to one ends of the plurality of the gate wirings, and a first detector connectable to the plurality of the first terminals and performing an abnormality detection operation of detecting an abnormality of a voltage supplied to the plurality of the gate wirings; and a second gate driver IC having a plurality of second terminals connected to another one of ends of the plurality of the gate wirings, and a second detector connectable to the plurality of the second terminals and performing an abnormality detection operation of detecting an abnormality of the voltage supplied to the plurality of the gate wirings.
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/HONG ZHOU/Primary Examiner, Art Unit 2629