DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/24/2025 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1: Claim(s) 1, 10, 14-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0167504 A1 Hasegawa et al in view of CN 209488674 U Bai in view of US 2020/0266707 A1 Kong et al.
2: As for Claim 1, Hasegawa et al teaches in Paragraphs [0021, 0025 and 0026] and depicts in Figure 10A An image capturing apparatus comprising: a first circuit board (1001) mounted with an image sensor (200); a second circuit board (1002) that is fixedly connected (via 110) to the first circuit board (1001) and supplies power (via 50) to the first circuit board (1001); a main circuit board (1003) that supplies power to the second circuit board (1002) (Paragraph [0089]); a flexible circuit board (700) connecting the main circuit board (1003) and the second circuit board (1002), and the second circuit board (1002) includes a stepdown circuit (50) that converts the first voltage into a second voltage (Paragraph [0026]). However, Hasegawa et al is silent as to the voltages used and does not teach the configuration of the DCDC converter.
Bai et al teaches on Page 4 an integrated camera with multiple circuit boards as depicted in Figure 1 and teaches a DCDC converter and teaches it is common for the voltage driving signals used for an image sensor (11) to be lower than the power supply voltage and teaches using the DCDC converter to perform a stepdown conversion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an image sensor that is driven by control signals with a lower voltage than the power supply as taught by Bai et al for the image sensor of Hasegawa et al since it was common for the voltage driving signals used for an image sensor to be lower than the power supply voltage and teaches using the DCDC converter to perform a stepdown conversion in order to decrease noise. Therefore, the combination teaches providing a voltage lower than the first voltage and outputs the second voltage to the image sensor via the flexible circuit board. However, Hasegawa et al in view of Bai et al does not teach the detailed circuit construction of the DCDC converter and does not teach the stepdown circuit is a DCDC converter including an inductor.
Kong et al depicts in Figure 1 and teaches in Paragraphs [0004] a DCDC converter including an inductor and teaches the configuration is advantageous because it improves response characteristics.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the DCDC converter of Kon et al for the DCDC converter of Hasegawa et al in view of Bai et al in order to improve the response characteristics.
3: As for Claim 10, Hasegawa et al teaches in Paragraph [0025] wherein a magnetic member (magnetic field is generated from the coils 104 and 203 is arranged between the first circuit board (1001) and the second circuit board (1002).
4: As for Claim 14, Kong et al further teaches in Paragraph [0004] wherein the stepdown circuit includes a linear regulator.
5: As for Claim 15, Kong et al further teaches in Paragraph [0004] wherein the stepdown circuit includes a switched capacitor (capacitive charge pump).
6: As for Claim 16, Paragraphs [0029] comprising; a second flexible circuit board (can be directly connected between 1001 and 1003) that connects the main circuit board (1003) and the first circuit board (1001), wherein the main circuit board (1003) sends a control signal for controlling the image sensor (200) to the first circuit board (1001) via the second flexible circuit board (1002), and receives image data acquired by the image sensor (200) via the second flexible circuit board (1002).
7: As for Claim 17, Hasegawa et al teaches in Paragraph [0025] wherein the image sensor is a CMOS image sensor.
8: As for Claim 19, Hasegawa et al teaches in Paragraph [0025] wherein the first circuit board is physically movable for image blur correction (camera shake correction).
9: Claim(s) 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0167504 A1 Hasegawa et al in view of CN 209488674 U Bai in view of US 2020/0266707 A1 Kon et al in view of Official Notice.
10: As for Claim 11, Hasegawa et al in view of Bai in view of Kon et al teaches multiple circuit boards with multiple processors connected to the circuit boards that generate heat, However, does not teach forming heat sings on the different processors in order to dissipate heat.
Official notice is taken that it was well known in the art before the effective filing date of the claimed invention form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise. Furthermore, this configuration will result in a heat dissipation member (heat sink) is arranged between (formed on chips 51) the first circuit board (1001) and the second circuit board (1002).
11: As for Claim 12, Hasegawa et al in view of Bai in view of Kon et al teaches multiple circuit boards with multiple processors connected to the circuit boards that generate heat, However, does not teach forming heat sings on the different processors in order to dissipate heat.
Official notice is taken that it was well known in the art before the effective filing date of the claimed invention form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise. Furthermore, this configuration will result in a heat dissipation member (heat sink) is arranged on a surface of one side of the second circuit board (1002).
12: As for Claim 13, Hasegawa et al in view of Bai in view of Kon et al teaches multiple circuit boards with multiple processors connected to the circuit boards that generate heat, However, does not teach forming heat sings on the different processors in order to dissipate heat.
Official notice is taken that it was well known in the art before the effective filing date of the claimed invention form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form heatsinks on processors in camera systems in order to dissipate heat and therefore, reduce noise. Furthermore, this configuration will result in the heat dissipation member (heat sink) is arranged on a surface of the second circuit board (1002), the surface facing (heatsink formed on 50) the main circuit board (1003).
13: As for Claim 18, Hasegawa et al in view of Bai in view of Kon et al teaches a camera system with a CMOS image sensor, However, does not teach wherein the image sensor is a CMOS image sensor of a stacked type in which a wiring layer for reading out a pixel signal is arranged on a back surface of a pixel.
Official notice is taken that it was well known in the art before the effective filing date of the claimed invention form CMOS image sensors in camera systems wherein the image sensor is a CMOS image sensor of a stacked type in which a wiring layer for reading out a pixel signal is arranged on a back surface of a pixel (back side illuminated) in order to improve image quality.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the CMOS image sensor of Hasegawa et al in view of Bai in view of Kon et al as a CMOS image sensor of a stacked type in which a wiring layer for reading out a pixel signal is arranged on a back surface of a pixel (back side illuminated) in order to improve image quality.
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M HANNETT whose telephone number is (571)272-7309. The examiner can normally be reached 8:00 AM-5:00 PM Monday thru Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/JAMES M HANNETT/Primary Examiner, Art Unit 2639
JMH
October 13, 2026
