DETAILED ACTION
In response to the communication filed on 09/18/2026, responded in following.
On this Office Action, claims 1-20, consisting of independent claims 1, 12, and 20.
Claims 1-20 are pending.
Claims 1-4, 12-15 and 20 are rejected under the 35 USC § 102.
Claims 5-11 and 16-19 are rejected under the 35 USC § 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 04/24/2025. These drawings are accepted.
Priority
The benefit of 63/638,616 filed on 04/25/2024 has been acknowledged.
Examiner’s Note
Although claims 6 and 10 recite the same additional limitation, they incorporate different limitations from their respective parent claims and therefore do not have identical scope (i.e., claim 5: Adder -> claim: 6 ALU; claim 9: AES -> claim: 10 ALU). Claim 17 and 18 are similar. No § 112(d) issue is identified for these claims.
Claim Objections
Claims 1, 3, 4, 12, 14, 15 and 20 are objected to because of the following informalities:
Claims 1,12 and 20 recite “receiving a peripheral response from the respective peripherals.” It should be “receiving respective peripheral responses from the respective peripherals.”
Claims 3 and 14 recite “wherein the respective peripherals comprise a decoder,… or another type of peripheral component.” It should be “wherein each of the respective peripherals comprise a decoder,… or another type of peripheral component.”
Claims 4 and 15 recite “a peripheral of the integrated circuit.” It should be “the peripheral of the integrated circuit.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 12-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”).
Regarding claim 1, SH discloses a method for providing active watermarking associated with an integrated circuit, the method comprising(SH: Fig. 1):
transmitting a challenge prompt to respective peripherals of an integrated circuit (SH: [0029] Still on the end-user side 2, this Figure shows a peripheral device 30 which is connected to the master 20 (including the processor “integrated circuit” in Fig. 3) through a so-called local data link 29 which is schematically shown by a bidirectional arrow; [0050] In variant, peripheral identification data 33 may be received from the peripheral device 30 upon request of the master device 20 (“transmitting a challenge prompt”, See para.[0073]-[0075] regarding a black list) or when the connection between these two devices 20, 30 is reset or needs to be re-established);
receiving a peripheral response from the respective peripherals in response to the challenge prompt (SH: [0031] the master device 20 receives from the peripheral device 30 (“receiving a peripheral response”), at least peripheral identification data 33 pertaining to the peripheral device 30); and
authenticating one or more functionalities of the integrated circuit based on the peripheral response from the respective peripherals (SH: [0032] the master device 20 generates a first mark 31 as a function of at least a part of said peripheral identification data 33 (“authenticating one or more functionalities”); [0034] Accordingly, any digital content received by the peripheral device is watermarked using a first mark based on peripheral identification data (“authenticating one or more functionalities based on the peripheral response”)).
Regarding claim 2, SH discloses all elements of the current invention as stated above. SH discloses the method of claim 1, further comprising:
modifying functionality of one or more portions of the integrated circuit in response to a determination that the peripheral response from the respective peripherals does not match an expected peripheral response for the respective peripherals (SH: [0034] If the peripheral identification data 33 are not received by the master device, the latter will be unable to watermark the digital content 11 and no content will delivered to the peripheral device from the master device).
Regarding claim 3, SH discloses all elements of the current invention as stated above. SH discloses the method of claim 1, wherein the respective peripherals comprise a decoder, an adder, an arithmetic logic unit (ALU), a cryptographic module, an advanced encryption standard (AES) module, an artificial intelligence accelerator, or another type of peripheral component (SH: [0028] this Figure shows a peripheral device 30 which is connected to the master 20 through a so-called local data link 29 which is schematically shown by a bidirectional arrow. The peripheral device 30 represents any device connectable to the master device 20 (“another type of peripheral component ")).
Regarding claim 4, SH discloses all elements of the current invention as stated above. SH discloses the method of claim 1, wherein transmitting the challenge prompt comprises transmitting, to a peripheral of the integrated circuit, an input signal associated with a memory address space for the peripheral (SH: [0068] At least one of the peripheral device identifier 36 and master device identifier 26 may relate to a device model number, a unique serial number, a subscriber identification number, a software version implemented in the relevant device, a network address or any value which may contribute (“a memory address space”) in identifying the source of the leakage).
Regarding claims 12 and 20, they are an apparatus and a non-transitory readable storage medium having a plurality of computer executable instructions that respectively corresponds to claim 1. Therefore, the claims are rejected for at least the same reasons.
Regarding claim 13, it is an apparatus claim that corresponds to claim 2. Therefore, the claim is rejected for at least the same reasons.
Regarding claim 14, it is an apparatus claim that corresponds to claim 3. Therefore, the claim is rejected for at least the same reasons.
Regarding claim 15, it is an apparatus claim that corresponds to claim 4. Therefore, the claim is rejected for at least the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Fudge et al. (US 20020191810 A1, hereinafter “Fudge”).
Regarding claim 5, SH discloses all elements of the current invention as stated above. However, SH does not disclose, Fudge, in a same field of endeavor, teaches the method of claim 1, wherein transmitting the challenge prompt comprises transmitting the challenge prompt via an adder of the integrated circuit (Fudge: [0096] The data output from the marking control block 436 are input to an adder 438 where they are added to the DCT coefficients for the luminance component of the image).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Fudge to transmit the challenge prompt comprises transmitting the challenge prompt via an adder of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because, in this way, the watermark data is applied to the image data while still in the DCT domain. Apart from the DC components, all DCT coefficients are considered as candidates for the application of watermark data (para. [0096]).
Regarding claim 16, it is an apparatus claim that corresponds to claim 5. Therefore, the claim is rejected for at least the same reasons.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Fudge et al. (US 20020191810 A1, hereinafter “Fudge”) as applied to claims above, and further in view of Zhang et al. (US 20090113536 A1, hereinafter “Zhang”).
Regarding claim 6, the combination of SH and Fudge discloses all elements of the current invention as stated above. However, the combination does not disclose, Zhang, in a same field of endeavor, teaches the method of claim 5, wherein transmitting the challenge prompt comprises transmitting the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit (Zhang: [0020] Processor 310 generally takes the form of hardware, software, and/or a combination of hardware and software that controls operation of system 300. "Processor", as used herein, refers generally to a computing device including a Central Processing Unit (CPU), such as a microprocessor. A CPU generally includes an arithmetic logic unit (ALU), which performs arithmetic and logical operations, and a control unit. The control unit extracts instructions (e.g., processor executable code) from memory and decodes and executes these instructions, calling on the ALU when necessary. Of course, other elements may be used, such as an electronic interface or Application Specific Integrated Circuit (ASIC), for example).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Zhang to transmit the challenge prompt comprises transmitting the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because an Arithmetic Logic Unit (ALU) is the core mathematical and decision-making brain inside a computer's Central Processing Unit (CPU), providing essential speed, precision, and efficiency for digital computing.
Regarding claim 7, the combination of SH, Fudge and Zhang discloses all elements of the current invention as stated above. SH discloses the method of claim 5, wherein transmitting the challenge prompt comprises transmitting the challenge prompt to a cryptographic module of the integrated circuit (SH: [0076] such a protection may be achieved by using any cryptographic process and/or using a secure channel, in particular for the return path 29. Such a cryptographic process may relate to symmetric or asymmetric encryption schemes involving the use of shared secret key or pairs of private and public keys).
Regarding claim 8, the combination of SH, Fudge and Zhang discloses all elements of the current invention as stated above. SH discloses the method of claim 5, wherein transmitting the challenge prompt comprises transmitting the challenge prompt to a decoder of the integrated circuit (Fudge: [0028] The decoder 144 inputs compressed information from the playback module 140 and performs decryption, decompression and formatting, and outputs the information to a projector 148 and a sound module 152).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Fudge to transmit the challenge prompt comprises transmitting the challenge prompt to a decoder of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because the decoder can provide decoding and decompressing the received signals responsive to the apparatus specific key to recover the data representing an image therefrom (para. [0013]).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Nakagata et al. (US 20120163583 A1, hereinafter “Nakagata”).
Regarding claim 9, SH discloses all elements of the current invention as stated above. However, SH does not disclose, Nakagata, in a same field of endeavor, teaches the method of claim 1, wherein transmitting the challenge prompt comprises transmitting the challenge prompt via an advanced encryption standard (AES) module of the integrated circuit (Nakagata: [0043] the shifting unit 22 generates a random number for every correcting codeword according to a random variate generation method such as a linear congruential generator, Mersenne twister, or a random number generation method using Advanced Encryption Standard (AES) encryption).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Nakagata to transmit the challenge prompt comprises transmitting the challenge prompt via an advanced encryption standard (AES) module of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because Advanced Encryption Standard (AES) offers robust data protection through a combination of high-level cryptographic security, processing speed, and global standardization.
Regarding claim 18, it is an apparatus claim that corresponds to claim 9. Therefore, the claim is rejected for at least the same reasons.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Nakagata et al. (US 20120163583 A1, hereinafter “Nakagata”) as applied to claims above, and further in view of Zhang et al. (US 20090113536 A1, hereinafter “Zhang”).
Regarding claim 10, the combination of SH and Nakagata discloses all elements of the current invention as stated above. However, the combination does not discloses, Zhang, in a same field of endeavor, teaches the method of claim 9, wherein transmitting the challenge prompt comprises transmitting the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit (Zhang: [0020] Processor 310 generally takes the form of hardware, software, and/or a combination of hardware and software that controls operation of system 300. "Processor", as used herein, refers generally to a computing device including a Central Processing Unit (CPU), such as a microprocessor. A CPU generally includes an arithmetic logic unit (ALU), which performs arithmetic and logical operations, and a control unit. The control unit extracts instructions (e.g., processor executable code) from memory and decodes and executes these instructions, calling on the ALU when necessary. Of course, other elements may be used, such as an electronic interface or Application Specific Integrated Circuit (ASIC), for example).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Zhang to transmit the challenge prompt comprises transmitting the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because an Arithmetic Logic Unit (ALU) is the core mathematical and decision-making brain inside a computer's Central Processing Unit (CPU), providing essential speed, precision, and efficiency for digital computing.
Regarding claim 19, the combination of SH and Nakagata discloses all elements of the current invention as stated above. However, the combination does not disclose, Zhang, in a same field of endeavor, teaches the apparatus of claim 18, wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
transmit the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit or a decoder of the integrated circuit (Zhang: [0020] Processor 310 generally takes the form of hardware, software, and/or a combination of hardware and software that controls operation of system 300. "Processor", as used herein, refers generally to a computing device including a Central Processing Unit (CPU), such as a microprocessor. A CPU generally includes an arithmetic logic unit (ALU), which performs arithmetic and logical operations, and a control unit. The control unit extracts instructions (e.g., processor executable code) from memory and decodes and executes these instructions, calling on the ALU when necessary. Of course, other elements may be used, such as an electronic interface or Application Specific Integrated Circuit (ASIC), for example).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Zhang to transmit the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit or a decoder of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because an Arithmetic Logic Unit (ALU) is the core mathematical and decision-making brain inside a computer's Central Processing Unit (CPU), providing essential speed, precision, and efficiency for digital computing.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Nakagata et al. (US 20120163583 A1, hereinafter “Nakagata”) as applied to claims above, and further in view of Fudge et al. (US 20020191810 A1, hereinafter “Fudge”)
Regarding claim 11, the combination of SH and Nakagata discloses all elements of the current invention as stated above. However, the combination does not disclose, Fudge, in a same field of endeavor, teaches the method of claim 9, wherein transmitting the challenge prompt comprises transmitting the challenge prompt to a decoder of the integrated circuit (Fudge: [0028] The decoder 144 inputs compressed information from the playback module 140 and performs decryption, decompression and formatting, and outputs the information to a projector 148 and a sound module 152).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Fudge to transmit the challenge prompt comprises transmitting the challenge prompt to a decoder of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because the decoder can provide decoding and decompressing the received signals responsive to the apparatus specific key to recover the data representing an image therefrom (para. [0013]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Stransky-Heilkron et al. (US 20220150565 A1, hereinafter “SH”) in view of Zhang et al. (US 20090113536 A1, hereinafter “Zhang”).
Regarding claim 17, SH discloses all elements of the current invention as stated above. However, the combination does not disclose, Zhang, in a same field of endeavor, teaches the apparatus of claim 16, wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
transmit the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit, a cryptographic module of the integrated circuit, or a decoder of the integrated circuit (Zhang: [0020] Processor 310 generally takes the form of hardware, software, and/or a combination of hardware and software that controls operation of system 300. "Processor", as used herein, refers generally to a computing device including a Central Processing Unit (CPU), such as a microprocessor. A CPU generally includes an arithmetic logic unit (ALU), which performs arithmetic and logical operations, and a control unit. The control unit extracts instructions (e.g., processor executable code) from memory and decodes and executes these instructions, calling on the ALU when necessary. Of course, other elements may be used, such as an electronic interface or Application Specific Integrated Circuit (ASIC), for example).
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have modified the master device for watermarking disclosed by SH with the teachings of Zhang to transmit the challenge prompt to an arithmetic logic unit (ALU) of the integrated circuit, a cryptographic module of the integrated circuit, or a decoder of the integrated circuit. One of ordinary skill in the art would have been motivated to make this modification because an Arithmetic Logic Unit (ALU) is the core mathematical and decision-making brain inside a computer's Central Processing Unit (CPU), providing essential speed, precision, and efficiency for digital computing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bucci et al. (US 20160094533 A1): [0065] FIG. 6 illustrates another image transformation consisting of modifying a source image (the top image, in this case the photograph of two sun loungers and a parasol on a beach) by adding three stars at the center of the image. The user therefore defines the transformation by requesting the addition of three stars at the center of the image, in the form of a watermark. The size of the stars is chosen randomly and the stars are chosen substantially at the center of the image (random positioning but close to the center). To make the transformation more complex to guess by a third party possibly spying on the exchanges, the secure electronic device is arranged to add many other elements (including other stars) in a completely random fashion. The user must check that, among all the elements added, there are indeed three stars towards the center. In FIG. 6, color not being enabled, the colors in the photograph are represented in gray shades and the colors of the edges of the added elements are represented schematically by various types of line (solid, broken).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW SUH whose telephone number is (571)270-5524. The examiner can normally be reached 9:00 AM- 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached at (571) 272-3862. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW SUH/Primary Examiner, Art Unit 2493
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