DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Paragraph [0001] on p. 1 of Applicant’s disclosure recites “…U.S. Patent Application No. 18/217,353, which was filed…U.S. Patent Application No. 17/868,438, which was filed…U.S. Patent Application No. 17/356,372, which was filed…U.S. Patent Application No. 16/670,800, which was filed…” where it should instead recite “…U.S. Patent Application No. 18/217,353, now U.S. Patent No. 12,307,252, which was filed…U.S. Patent Application No. 17/868,438, now U.S. Patent No. 11,734,006, which was filed…U.S. Patent Application No. 17/356,372, now U.S. Patent No. 11,436,014, which was filed…U.S. Patent Application No. 16/670,800, now U.S. Patent No. 11,080,056, which was filed…”
Appropriate correction is required.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 2 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,307,252. This is a statutory double patenting rejection.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 12,307,252, as shown in the table below. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claim is broader in every aspect than the patent claim and is therefore an obvious variant thereof. Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 2, and 5 of U.S. Patent No. 11,734,006; Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-2 of U.S. Patent No. 11,436,014; and Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1 and 3 of U.S. Patent No. 11,080,056, as shown in the tables below. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application claims are essentially covered by the limitations of the patent claims.
19/188,630
Claim 1
2
12,307,252
Claim 1
1
11,734,006
Claims 1-2
5
11,436,014
Claims 1-2
1
11,080,056
Claims 1, 3
1
19/188,630 (Claim 1)
12,307,252 (Claim 1)
A processor comprising:
A processor comprising:
a register file:
a register file:
comprising a set of banks; and
comprising a set of banks;
configured to store image data;
configured to store image data; representing a two-dimensional register abstraction;
an interconnect unit configured to:
an interconnect unit configured to:
access a set of image data stored in the register file; and
access a set of image data stored in the register file; and
access a set of stencil data for the set of image data; and
access a set of stencil data for the set of image data; and
a set of logic units:
a set of logic units:
in communication with the interconnect unit;
in communication with the interconnect unit;
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
19/188,630 (Claim 1)
11,734,006 (Claims 1-2)
A processor comprising:
A processor comprising: (Claim 1)
a register file: comprising a set of banks; and
a banked register file (Claim 1)
configured to store image data;
configured to store image pixel data; (Claim 1)
an interconnect unit configured to:
an interconnect unit configured to (Claim 1)
access a set of image data stored in the register file; and
access: multiple subsets of the image pixel data from the banked register file; and (Claim 1)
access a set of stencil data for the set of image data; and
corresponding stencil data for the multiple subsets of image pixel data; and (Claim 1)
a set of logic units: in communication with the interconnect unit;
a set of arithmetic logic units (Claim 1)
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to concurrently execute a set of one-dimensional stencil operations on subsets of the image pixel data and corresponding stencil data, the set of one-dimensional stencil operations representing a multi-dimensional stencil operation (Claim 1)
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
configured to concurrently execute a set of smaller convolution operations on each subset of the image pixel data and corresponding stencil data, the set of smaller convolution operations: characterized by a set of smaller kernel sizes (Claim 2)
19/188,630 (Claim 1)
11,436,014 (Claims 1-2)
A processor comprising:
A processor comprising: (Claim 1)
a register file:
a banked register file: (Claim 1)
comprising a set of banks; and
comprising a set of register banks; and (Claim 1)
configured to store image data;
configured to store image pixel data (Claim 1)
an interconnect unit configured to:
the interconnect unit configured to (Claim 1)
access a set of image data stored in the register file; and
access: multiple subsets of the image pixel data from the banked register file; and (Claim 1)
access a set of stencil data for the set of image data; and
corresponding stencil data for the multiple subsets of image pixel data; and (Claim 1)
a set of logic units:
a set of arithmetic logic units (Claim 1)
in communication with the interconnect unit;
in communication with the interconnect unit (Claim 1)
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to concurrently execute a set of smaller stencil operations on each subset of the image pixel data and the corresponding stencil data, the set of smaller stencil operations representing a larger stencil operation characterized by greater than two dimensions (Claim 1)
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
configured to concurrently execute a set of smaller convolution operations on each subset of the image pixel data and the corresponding stencil data, the set of smaller convolution operations: characterized by a set of smaller kernel sizes (Claim 2)
19/188,630 (Claim 1)
11,080,056 (Claims 1 and 3)
A processor comprising:
A processor comprising: (Claim 1)
a register file:
a banked register file: (Claim 1)
comprising a set of banks; and
comprising a set of register banks; (Claim 1)
configured to store image data;
configured to store image pixel data (Claim 1)
an interconnect unit configured to:
the interconnect unit configured to: (Claim 1)
access a set of image data stored in the register file; and
access multiple subsets of the image pixel data from the banked register file, (Claim 1)
access a set of stencil data for the set of image data; and
access corresponding stencil data (Claim 1)
a set of logic units:
a set of arithmetic logic units (Claim 1)
in communication with the interconnect unit;
in communication with the interconnect unit (Claim 1)
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to concurrently execute a set of operations on each subset of the image pixel data and the corresponding stencil data, the set of operations representing a larger stencil operation characterized by the larger two-dimensional stencil pattern (Claim 1)
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
configured to concurrently execute a set of convolution operations characterized by a set of smaller kernel sizes based on the multiple subsets of image pixel data and the corresponding stencil data (Claim 3)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hameed (US 20150086134A1) in view of Keall (US 20080291208A1).
Hameed teaches a processor (40, Fig. 4) comprising: a register file; and configured to store image data (convolution image processor 40 includes a shift register unit 44, stores image pixel data and stencil data to various register files, [0045]); an interconnect unit (62) configured to: access a set of the image data stored in the register file; and access a set of stencil data for the set of image data; and a set of logic units (60): in communication with the interconnect unit; configured to execute a set of stencil operations on the set of image data and the set of stencil data (horizontal IF 58B may be coupled to the 1-dimensional shift register 52 and configured to provide multiple shifted versions of a row of image pixel data from the 1-dimensional shift register 52 to a first input 62A of the ALUs 60, column IF 58C may be coupled to the 2-dimensional shift register 54 and configured to provide multiple shifted versions of a column of image pixel data from the 2-dimensional shift register 54 to the first input 62A of the ALUs 60, first 2-dimensional IF 58D may be coupled to the 2-dimensional shift register 54 and configured to provide multiple shifted versions of a 2-dimensional block of image pixel data from the 2-dimensional shift register 54 to the first input 62A of the ALUs 60, 1-dimensional IF 58E may be coupled to the 2-dimensional stencil register 56 and configured to provide multiple shifted versions of a 1-dimensional block of stencil data from the 2-dimensional stencil register 56 to a second input 62B of the ALUs 60, second 2-dimensional IF 58 F may be coupled to the 2-dimesional stencil register 56 and configured to provide multiple shifted versions of a 2-dimesional block of stencil data from the 2-dimensional stencil register 56 to the second input 62B of the ALUs 60, [0050], ALUs 60 may be configured to perform arithmetic operations such as multiplication on a given image pixel and stencil value, [0051], multiplying each image pixel in the array of image pixel data by a corresponding stencil value in the stencil data, [0034]). Hameed teaches even though finding the scale-space extrema is a 3-dimensional stencil computation, the problem can be converted into a 2-dimensional stencil operation by interleaving rows from different images into a single buffer [0038]. Convolution involves translating stencil data across an array of image pixel data, multiplying each image pixel in the array of image pixel data by a corresponding stencil value in the stencil data, and adding the resulting values together. Hameed teaches 1-dimensional convolution [0034]. Thus, it would have been obvious to one of ordinary skill in the art that a 2-dimensional stencil operation [0038] spans a first size range, and a 1-dimensional convolution [0034] spans a second size range different from the first size range, since a 2-dimensional size range would be different from a 1-dimensional size range. Thus, Hameed teaches the set of stencil operations spanning a first size range and characterized by at least two-dimensions [0038]; and configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from the first size range [0034].
However, Hameed does not teach that the register file comprises a set of banks. However, Keall teaches a register file: comprising a set of banks; and configured to store image data (vector register file (VRF), [0025], VRF 235 comprises a plurality of pixel banks, [0050], concurrently access pixel data in the VRF Bank_0 235a, [0054]). Thus, this teaching from Keall can be implemented into the register file of Hameed so that the register file comprises a set of banks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hameed so that the register file comprises a set of banks because Keall suggests that this way, while pixel data is being written to one of the banks, the pixel data in the other banks can be processed, and thus this increases the processing speed [0052].
Allowable Subject Matter
Claim 2 is rejected under double patenting, but would be allowable if terminal disclaimers are filed and Claim 2 is rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art taken singly or in combination do not teach or suggest the combination of all the limitations of Claim 2 and base Claim 1, and in particular, do not teach wherein the register file represents a two-dimensional register abstraction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONI HSU whose telephone number is (571)272-7785. The examiner can normally be reached M-F 10am-6:30pm.
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JH
/JONI HSU/Primary Examiner, Art Unit 2611
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