Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a restriction requirement dated January 8, 2026, the Applicants elected group 1 of claims 1-9 without traverse in a reply filed on October 13, 2025. The non-elected claims 10-20 are withdrawn.
Pending elected claims 2-9 of which claim 1 is an independent claim, are examined on their merits, infra
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2024-0055681 filed in Korea on April 25, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted April 24, 2025.
Information Disclosure Statement
The Applicant’s Information Disclosure Statement filed (April 24, 2025 and August 26, 2025) has been received, entered into the record, and considered.
Drawings
The drawings filed April 24, 2025 are accepted by the examiner.
Abstract
The abstract filed April 24, 2025 is accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
7. Claims 1-9 in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “configured” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “configured” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the words “a first light-emitting element configured to, a first driving transistor configured to, a second light-emitting element configured to, a second driving transistor configured to” in claim 1, and “a third light-emitting element configured to, a third driving transistor configured to” in claim 5, with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20250113705 A1) in view of Lee (US 20250311605 A1).
As to Claim 1:
Wu et al. discloses a display device (Wu, see Abstract, where Wu discloses a display substrate and a display device. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is arranged in a same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, the display substrate satisfies a following relationship: a value range of (W*L+S2)*Ml/M2 is [0.014, 0.133], and a value range of S2/(W*L) is [2.82, 28.85], where W is a width of the channel of the driving transistor, L is a length of the channel of the driving transistor, S2 is a facing area between the second electrode plate and the first electrode plate, Ml is a count of pixel openings in the display substrate, and M2 is an area of the display substrate, thus increasing the facing area between the electrode plates of the storage capacitor, increasing the capacitance, and improving the holding capacity of the capacitor, and being beneficial to increasing the area ratio of the storage capacitor to the pixel opening, increasing the area proportion of the storage capacitor, and improving the display quality) comprising: a first subpixel (Wu, see paragraph [0264], where Wu discloses a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103) including a first light-emitting element configured to emit light of a first color (Wu, see paragraph [0116], where Wu discloses that the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 have different light-emitting colors); and a first driving transistor configured to drive the first light-emitting element (Wu, see paragraph [0196], where Wu discloses that referring to FIG. 3-FIG. 11, the embodiment of the present disclosure provides a display substrate, which includes a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst includes a first electrode plate Ca and a second electrode plate Cb, the first electrode plate Ca of the storage capacitor Cst is connected to the gate electrode T3g of the driving transistor T3, and the second electrode plate Cb of the storage capacitor Cst is connected to the first electrode T3a of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a is configured to drive the light-emitting element 100b, the sub-pixel 100 includes a pixel opening PO, and the pixel opening PO is configured to define a light-emitting region of the sub-pixel 100); a second subpixel (Wu, see paragraph [0264], where Wu discloses a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103) including a second light-emitting element configured to emit light of a second color (Wu, see paragraph [0116], where Wu discloses that the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 have different light-emitting colors); and a second driving transistor configured to drive the second light-emitting element (Wu, see paragraph [0196], where Wu discloses that referring to FIG. 3-FIG. 11, the embodiment of the present disclosure provides a display substrate, which includes a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst includes a first electrode plate Ca and a second electrode plate Cb, the first electrode plate Ca of the storage capacitor Cst is connected to the gate electrode T3g of the driving transistor T3, and the second electrode plate Cb of the storage capacitor Cst is connected to the first electrode T3a
of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a is configured to drive the light-emitting element 100b, the sub-pixel 100 includes a pixel opening PO, and the pixel opening PO is configured to define a light-emitting region of the sub-pixel 100), at least one first dummy hole disposed in the first driving transistor (Wu, see paragraphs [0052] and [0334], where Wu discloses that the driving transistor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, a dummy sub-pixel is arranged in a vicinity of an edge of the display substrate, the dummy sub-pixel is provided with a dummy driving transistor and a first dummy reset transistor, the first dummy reset transistor is connected to a gate electrode of the dummy driving transistor, the first dummy reset transistor is disconnected from the first initialization line. It is noted that in order to make the second electrode of the dummy light-emitting control transistor dT5 and the second electrode of the dummy driving transistor dT3 connected, it is necessary to provide a via hole at the corresponding position, the same situation applies as at other positions); and at least one second dummy hole disposed in the second driving transistor transistor (Wu, see paragraphs [0052] and [0334], where Wu discloses that the driving transistor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, a dummy sub-pixel is arranged in a vicinity of an edge of the display substrate, the dummy sub-pixel is provided with a dummy driving transistor and a first dummy reset transistor, the first dummy reset transistor is connected to a gate electrode of the dummy driving transistor, the first dummy reset transistor is disconnected from the first initialization line. It is noted that in order to make the second electrode of the dummy light-emitting control transistor dT5 and the second electrode of the dummy driving transistor dT3 connected, it is necessary to provide a via hole at the corresponding position, the same situation applies as at other positions).
Wu differs from the claimed subject matter in that Wu does not explicitly disclose wherein a total aperture area of the at least one first dummy hole of the first driving transistor is different than a total aperture area of the at least one second dummy hole of the second driving transistor.
However in an analogous art, Lee discloses wherein a total aperture area of the at least one first dummy hole of the first driving transistor is different than a total aperture area of the at least one second dummy hole of the second driving transistor (Lee, see paragraphs [0016] and [0017], where Lee discloses that each of the driving opening and the dummy opening may have a shape substantially of a circle, a shape substantially of an oval, a shape substantially of a rectangle, or a shape of a rectangle having a substantially rounded corner, when viewed in a plan view. a minimum distance between the dummy opening and the light emission opening may be about less than or about equal to a minimum distance between the driving opening and the dummy opening, the different shapes teach or suggest a different total aperture area).
It would have been obvious to one of ordinary skill in the art to modify the invention of Wu with Lee. One would be motivated to modify Wu by disclosing wherein a total aperture area of the at least one first dummy hole of the first driving transistor is different than a total aperture area of the at least one second dummy hole of the second driving transistor as taught by Lee, and thereby providing a display device improved in display quality by preventing a non-display region adjacent to an end of the display region to be viewed differently from another portion of the display surface. (Lee, see paragraph [0007]).
As to Claim 2:
Wu in view of Lee discloses that the display device of claim 1, wherein the total aperture area of the at least one first dummy hole of the first driving transistor is larger than the total aperture area of the at least one second dummy hole of the second driving transistor (Lee, see paragraphs [0016] and [0017], where Lee discloses that each of the driving opening and the dummy opening may have a shape substantially of a circle, a shape substantially of an oval, a shape substantially of a rectangle, or a shape of a rectangle having a substantially rounded corner, when viewed in a plan view. a minimum distance between the dummy opening and the light emission opening may be about less than or about equal to a minimum distance between the driving opening and the dummy opening, the different shapes teach or suggest a different total aperture area).
As to Claim 3:
Wu in view of Lee discloses that the display device of claim 1, wherein a number of the at least one first dummy hole of the first driving transistor is greater than a number of the at least one second dummy hole of the second driving transistor (Lee, see paragraphs [0016] and [0017], where Lee discloses that each of the driving opening and the dummy opening may have a shape substantially of a circle, a shape substantially of an oval, a shape substantially of a rectangle, or a shape of a rectangle having a substantially rounded corner, when viewed in a plan view. a minimum distance between the dummy opening and the light emission opening may be about less than or about equal to a minimum distance between the driving opening and the dummy opening, the different shapes teach or suggest a different total aperture area).
As to Claim 4:
Wu in view of Lee discloses that the display device of claim 1, wherein the first subpixel further includes at least one peripheral dummy hole disposed in an insulating layer around the first driving transistor (Lee, see paragraph [0013], where Lee discloses that the dummy part may be directly disposed on the uppermost layer among the plurality of insulating layers).
Allowable Subject Matter
Claims 5, 6, 7, 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 5 and dependent claims 6-9, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “comprising: a third subpixel including a third light-emitting element configured to emit light of a third color and a third driving transistor configured to drive the third light-emitting element; and at least one third dummy hole disposed in the third driving transistor, wherein a total aperture area of the at least one third dummy hole of the third driving transistor is the same as any one of the total aperture area of the first dummy hole of the first driving transistor and the total aperture area of the at least one second dummy hole of the second driving transistor, or is different from the total aperture area of the at least one first dummy hole of the first driving transistor and the total aperture area of the at least one second dummy hole of the second driving transistor”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Lim (US 20230052275 A1) discloses a display apparatus includes a first substrate including a display area and a non-display area surrounding the display area, a second substrate on the first substrate, a bank in which a first opening in the display area and a first dummy opening in the non-display area are defined, a first quantum dot layer filling the first opening, and a first dummy quantum dot layer filling the first dummy opening, where each of the first quantum dot layer and the first dummy quantum dot layer includes first quantum dots and first scatterers.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624