DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Chinese parent Application No. CN202211314271.5, filed on October 25, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 30, 2025 and November 3, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon, United States Patent Application Publication No. US 2022/0066881 A1.
Regarding claim 1, Jeon discloses an electronic device (Fig. 1, generally, Summary) comprising:
a touch display panel (Fig. 1, display touch panel, #10; Detailed Description, [0031-0035]);
a timing controller coupled to the touch display panel and configured to provide a timing control signal for the touch display panel (Fig. 1, application processor, #40; Detailed Description, [0031-0045]; See also Fig. 2and SCLK; Detailed Description, [0054], “In FIG. 2, the application processor 40 includes a hold signal terminal which provides the hold signal HOLD#, a chip select signal terminal which provides the chip select signal CS#, a serial clock signal terminal which provides a serial clock signal SCLK, “) ;
a circuit board, coupled to the touch display panel (Fig. 1, touch integrated circuit, #30; inherent that touch integrated circuit will have a circuit board);
a touch integrated circuit disposed on the circuit board and configured to provide a touch signal for the touch display panel (Fig. 1, touch integrated circuit, #30; Detailed Description, [0040-0050], “In order to perform the touch function, the touch integrated circuit 30 is configured to provide a touch driving signal Tx for sensing a touch, to the display touch panel 10, and receive a touch sensing signal Rx having sensed a touch.”); and a
non-volatile memory disposed outside the touch integrated circuit, coupled to the timing controller and the touch integrated circuit, and configured to provide a non-volatile storage function for both the timing controller and the touch integrated circuit (Fig. 1, flash memory, #50; Detailed Description. [0041-0050], “The flash memory 50 may be configured to store touch firmware and the flash data for the operation of the touch integrated circuit 30 and provide the flash data in response to reading by the touch integrated circuit 30….or example, the application processor 40 may be configured to provide an enabled hold signal HOLD# and a disabled chip select signal CS# for resetting, to the flash memory 50, in order to allow the flash memory 50 to perform the reset operation. “; See also Figs. 2-3 for particular connection between flash memory and application processor) .
Regarding claim 2, Jeon discloses the electronic device further comprising an arbitration controller configured to schedule the timing controller or the touch integrated circuit to communicate with the non-volatile memory (Figs. 1-3, chip select signal providing circuit, #44; Detailed Description, [0041-0060], “For example, the application processor 40 may be configured to provide an enabled hold signal HOLD# and a disabled chip select signal CS# for resetting, to the flash memory 50, in order to allow the flash memory 50 to perform the reset operation…. The chip select signal CS# maintains a high level deactivated state when an access to the flash memory 50 is not necessary, and transitions to a low level activated state at a time when an access to the flash memory 50 is necessary to reset the flash data.”)
Regarding claim 4, Jeon discloses the electronic device, further comprising a display driver integrated circuit, wherein the timing controller and/or the arbitration controller are/is integrated into the display driver integrated circuit (Fig. 1-3, display integrated circuit, #20; Detailed Description, [0045-0059], “The application processor 40 may synchronize display and touch by being interfaced with the display integrated circuit 20 and the touch integrated circuit 30.”).
Regarding claim 5, Jeon discloses wherein the timing controller is disposed on the circuit board, and wherein the arbitration controller is integrated into the timing controller (Figs. 1-3, chip select signal providing circuit, #44; Detailed Description, [0041-0060]; Fig. 3 shows chip select signal providing circuit 44 integrated into application processor 40).
Regarding claim 6, Jeon discloses the electronic device, further comprising an enable control line coupled to the timing controller and the touch integrated circuit and is configured to select and enable the timing controller or the touch integrated circuit to perform signal transmission with the non-volatile memory (Figs. 1-3, HOLD#; Detailed Description, [0047-0060], “For example, the application processor 40 may be configured to provide an enabled hold signal HOLD# and a disabled chip select signal CS# for resetting, to the flash memory 50, in order to allow the flash memory 50 to perform the reset operation.”).
Regarding claim 12, Jeon discloses wherein the non-volatile memory comprises a flash memory (Fig. 1, flash memory, #50; Detailed Description, [0041-0050]).
Regarding claim 13, Jeon discloses wherein the non-volatile memory is disposed on the circuit board (Fig. 1, flash memory, #50; Detailed Description, [0041-0050]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Tang, United States Patent Application Publication No. US 2019/0354218 A1.
Regarding claim 14, Jeon discloses the electronic device further comprising a display driver integrated circuit (Fig. 1-3, display integrated circuit, #20; Detailed Description, [0045-0059])
Jeon does not explicitly disclose wherein the timing controller and the non-volatile memory are integrated into the display driver integrated circuit
Tang, on a similar field of endeavor, discloses an electronic device comprising a display driver integrated circuit wherein the timing controller and the non-volatile memory are integrated into the display driver integrated circuit (Fig. 1-5, Detailed Description, [0038-0050], “The touch controller 130 includes a storage device 132, e.g. a flash memory, for storing the touch information …Each of the display driving channels 314 and 324, for example, includes an output buffer. In the present embodiment, the touch controller 130 and the timing controller 332 may be implemented in the same integrated-circuit chip or separate integrated-circuit chips.”).
It would have been obvious to one of ordinary skill in the art to have modified the display driver integrated circuit within Jeon to include the suggestions and teachings of Tang to provide wherein the timing controller and the non-volatile memory are integrated into the display driver integrated circuit. The motivation to combine these arts is to utilize a same integrated chip circuit (See Tang, Detailed Description, [0045-0048]) as a matter of design choice and to make parts integral (See MPEP 2144.04 Part V).
Regarding claim 16, Jeon in combination with Tang discloses or suggest every element of claim 14 and Jeon further discloses wherein the touch integrated circuit comprises a first communication interface, wherein the non-volatile memory comprises a second communication interface, and wherein the electronic device further comprises a protocol converter is configured to match the first communication interface with the second communication interface (Fig. 2-3, flash memory #50; and application processor, #40; Detailed Description, [0053-0070], “The application processor 40 and the flash memory 50 may be configured to be interfaced as illustrated in FIG. 2.”).
Thus, it would have remained obvious to combine Jeon and Tang in the manner of claim 14.
Regarding claim 17, Jeon in combination with Tang discloses or suggest every element of claim 16 and Jeon further discloses wherein the touch integrated circuit comprises a serial peripheral interface, wherein the non-volatile memory comprises a memory interface, and wherein the serial peripheral interface is coupled to the memory interface through the protocol converter (Figs. 1-3, Detailed Description, [0040-0070], “The touch integrated circuit 30 is configured to use flash data of the flash memory 50 which stores touch firmware, at a booting time or a display-on time of the mobile phone…. Therefore, the touch integrated circuit 30 is configured to read the flash data at the booting time or the display-on time of the mobile phone, provide the touch driving signal Tx for sensing a touch, to the display touch panel 10, by using the flash data, and receive the touch sensing signal Rx having sensed a touch, from the display touch panel 10… n FIG. 2, the flash memory 50 includes a power terminal to which an operating voltage VCC is applied, a hold signal terminal which receives the hold signal HOLD#, a chip select signal terminal which receives the chip select signal CS#, a serial clock signal terminal which receives the serial clock signal SCLK, a serial input signal terminal which receives the serial input signal SI, a serial output signal terminal which provides the serial output signal SO, a write protection signal terminal which receives the write protection signal WP#, and a ground terminal to which a ground voltage GDN is applied.”).
Thus, it would have remained obvious to combine Jeon and Tang in the manner of claim 14.
Regarding claim 18, Jeon in combination with Tang discloses or suggest every element of claim 16 and Jeon further discloses wherein the protocol converter is integrated into the display driver integrated circuit or the timing controller (Detailed Description, [0053-0070], “The application processor 40 and the flash memory 50 may be configured to be interfaced as illustrated in FIG. 2… in the application processor 40 and the flash memory 50, the hold signal terminals for the hold signal HOLD#, the chip select signal terminals for the chip select signal CS#, the serial clock signal terminals for the serial clock signal SCLK, the serial input signal terminals for the serial input signal SI, the serial output signal terminals for the serial output signal SO and the write protection signal terminals for the write protection signal WP# are interfaced to be connected with each other for signal transfer” See Figs. 2-3—it in inherent the interface of the flash memory and application processor include an interfaced signal converter for signal transfer).
Thus, it would have remained obvious to combine Jeon and Tang in the manner of claim 16.
Regarding claim 19, Jeon in combination with Tang discloses or suggest every element of claim 14 and Jeon further discloses wherein the non-volatile memory comprises wherein the non-volatile memory comprises providing a non-volatile storage function for the timing controller (See Fig. 2 and Detailed Description, [0044-0059], “n FIG. 2, in the application processor 40 and the flash memory 50, the hold signal terminals for the hold signal HOLD#, the chip select signal terminals for the chip select signal CS#, the serial clock signal terminals for the serial clock signal SCLK, the serial input signal terminals for the serial input signal SI, the serial output signal terminals for the serial output signal SO and the write protection signal terminals for the write protection signal WP# are interfaced to be connected with each other for signal transfer.”) and provide the non-volatile storage function for the touch integrated circuit (See detailed Description, [0040-0050], “The flash memory 50 may be configured to store touch firmware and the flash data for the operation of the touch integrated circuit 30 and provide the flash data in response to reading by the touch integrated circuit”)
Jeon and Tang do not explicitly disclose wherein the non-volatile memory comprises: a first non-volatile storage area is configured to provide the non-volatile storage function for the timing controller; and a second non-volatile storage area configured to provide the non-volatile storage function for the touch integrated circuit.
However, it would have been obvious to one of ordinary skill in the art to have modified the memory within the combination of Jeon and Tang to provide wherein the non-volatile memory comprises: a first non-volatile storage area is configured to provide the non-volatile storage function for the timing controller; and a second non-volatile storage area configured to provide the non-volatile storage function for the touch integrated circuit. The motivation to combine these arts is to make separable the memory storage aspects of the timing controller and touch integrated circuit, which would have been pursued by one of ordinary skill without undue experimentation (See MPEP 2144.04 Part V).
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Komatsu et al., United States Patent Application Publication No. US 2021/0072843 A1.
Regarding claim 15, Jeon discloses every element of claim 1 and further discloses
wherein the timing controller is disposed on the circuit board. (Jeon, Fig. 1, generally, Summary)
Jeon does not explicitly disclose wherein the non-volatile memory is integrated into the timing controller.
Komatsu, in a similar field of endeavor, disclose an electronic device wherein the non-volatile memory is integrated into the timing controller (Fig. 1, host processor, #5, memory, #42; Detailed Description, [0044-0050], “The host processor 5 is connected to the bus interfaces 40 and 41 and to the memory 42 via the internal bus 6. The memory 42 stores programs that define the operations of the host processor 5. The host processor 5 reads and executes these programs in order to perform processes, to be discussed later. The memory 42 further plays the role of temporarily or permanently storing diverse data for use by the host processor 5 during processing”).
It would have been obvious to one of ordinary skill in the art to have modified the timing controller and non-volatile memory within Jeon to include the suggestions and teachings of Komatsu to provide wherein the non-volatile memory is integrated into the timing controller. The motivation to combine these arts is to utilize an internal bus (See Komatsu, Detailed Description, [0044]]) as a matter of design choice and to make parts integral (See MPEP 2144.04 Part V).
Allowable Subject Matter
Claims 3, 7-11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record does not disclose wherein the arbitration controller is further configured to: determine whether the timing controller accesses the non-volatile memory; block the touch integrated circuit from communicating with the non-volatile memory when the timing controller accesses the non-volatile memory; and schedule the touch integrated circuit to communicate with the non-volatile memory when the timing controller does not access the non-volatile memory.
Regarding claim 7, the prior art of record does not disclose the electronic device further comprising a display driver integrated circuit, wherein the timing controller is integrated into the display driver integrated circuit, wherein the display driver integrated circuit comprises a first communication interface, wherein the touch integrated circuit comprises a second communication interface, wherein the non-volatile memory is coupled to the first communication interface and the second communication interface, wherein two ends of the enable control line are coupled to the display driver integrated circuit and the touch integrated circuit, wherein the enable control line comprises a first control line and a second control line, wherein the display driver integrated circuit is configured to control the first communication interface to be in a first high-impedance state when the first control line is valid, and wherein the touch integrated circuit is configured to control the second communication interface to be in a second high-impedance state when the second control line is valid.
Regarding claim 9, the prior art of record does not disclose wherein the timing controller is disposed on the circuit board and comprises a first communication interface, wherein the touch integrated circuit comprises a second communication interface, wherein the non-volatile memory is coupled to the first communication interface and the second communication interface, wherein two ends of the enable control line are coupled to the timing controller and the touch integrated circuit, wherein the enable control line comprises a first control line and a second control line, wherein the timing controller is configured to control the first communication interface to be in a first high-impedance state when the first control line is valid, and wherein the touch integrated circuit is configured to control the second communication interface to be in a second high-impedance state when the second control line is valid.
The cited references do not teach the entirety of the structural, functional, conditional and relational aspects of dependent claims 3, 7 or 9 above, in combination with the base elements of independent claim 1 and intervening claims. Further reasons for allowance may be given in a Notice of Allowance.
The remaining claims are dependent off of claim 3, 7 or 9 and are objected to as allowable as a result of their dependencies.
Other References
The following references are also cited as relevant on the PTO-892 but may not be specifically relied upon within this Action:
Ahn (US 2021/0255753 A1)
Zhu et al (US 2019/0258539 A1)
Conclusion
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/KWIN XIE/Primary Examiner, Art Unit 2626