DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8, 15-17, & 19 are objected to because of the following informalities:
Claim 8, line 4, “unit-gain amplifier” is expected to read “unity-gain amplifier”
Claim 15, line 5, “unit-gain amplifier” is expected to read “unity-gain amplifier”
By virtue of their dependency on claim 15, claims 16-17 are also objected to.
Claim 19, line 3, “unit-gain amplifier” is expected to read “unity-gain amplifier”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the phase detector" in line 5. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the phase detector” to read “the second phase detector”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0403620 A1), hereinafter Wang, in view of Hossain et al. (US 2019/0253049 A1), hereinafter Hossain.
Regarding claim 1, Wang discloses, in figure 2 & 3, a cascaded phase-locked loop (PLL) system, comprising:
a first stage comprising a type-II loop (PLL 202), wherein the first stage is configured to operate at a first operation frequency (operation frequency of 900MHz); and
a second stage comprising a dual-path loop (SSPLL 206), wherein the second stage is configured to operate at a second operation frequency (operation frequency of 40.5GHz);
wherein a ratio of the second operation frequency to the first operation frequency is an integer greater than 2 (ratio of the second operation frequency of 40.5GHz to the first operation frequency of 900MHz is greater than 2), but does not explicitly disclose the second stage comprising a dual-path loop.
However, Hossain discloses, in figure 5, the second stage comprising a dual-loop path (see figure 5 disclosing the second stage PLL with a proportional path 558 and integral path 560).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dual-path loop of Hossain in the second stage of Wang, to achieve the benefit of implementing a second PLL that cancels or minimizes a jitter from the output of the first PLL (Hossain, Para [0037]).
Regarding claim 2, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, and Wang continues to disclose, in figure 2 & 3, wherein the type-II loop includes a voltage-controlled oscillator (VCO), a phase detector, a charge pump, a second-order loop filter, and a divider (Para [0015], “the PLL includes a forward path, which feeds the reference signal through a phase-frequency detector (PFD) to produce an error signal, wherein a charge pump converts the error signal into a voltage, which feeds through a loop filter and is used to tune a voltage-controlled oscillator to produce the IF signal. It also includes a feedback path, which feeds the IF signal through a frequency divider to produce a feedback signal.”).
Regarding claim 3, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, and Hossain continues to disclose, in figure 5, wherein the dual-path loop includes a proportional path and an integral path (see figure 5 disclosing the second stage PLL with a proportional path 558 and integral path 560).
Regarding claim 12, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, and Hossain continues to disclose, in figure 2 & 5, wherein the first stage further comprises a frequency-locked loop (Para [0027], “Modulator 240 selects between the possible phases such that an average phase over time is added by phase interpolator 236 to achieve the desired frequency specified by frequency selection signal 242”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Hossain as applied to claims 1-3 & 12 above, and further in view of Martin et al. (US 8,170,169 B2), hereinafter Martin.
Regarding claim 4, Wang in view of Hossain disclose the cascaded PLL system according to claim 3, but do not explicitly disclose wherein the proportional path includes a passive loop filter, and wherein the integral path includes a charge pump and a loop filter.
However, Martin discloses, in figure 4, wherein the proportional path includes a passive loop filter (Col. 6, Lines 45-50, “proportional path…passive filter [430]”), and wherein the integral path includes a charge pump and a loop filter (Col. 6, Lines 45-50, “integral path…integral charge pump I_CP 450…integral loop filter I_LF 460”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dual-path loop of Martin in the second stage of Wang and Hossain, to achieve the benefit of allowing the proportional path to have a relatively large current and therefore lower impedance in its passive filter components, resulting in reduced noise in the signal and improved jitter performance (Martin, Col. 7, Lines 7-27).
Claims 5 & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Hossain as applied to claims 1-3 & 12 above, and further in view of Garlepp et al. (US 2006/0001494 A1), hereinafter Garlepp.
Regarding claim 5, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, and Wang continues to disclose, in figure 2 & 3, wherein the first stage comprises a first voltage-controlled oscillator (VCO) having a first tuning range (Para [0039], “PLL 202 operates at relatively low frequency. Also, because the IF value is not constrained by any noise-based optimization, it can be selected based on a millimeter wavelength VCO tuning range”);
wherein the second stage comprises a second VCO having a second tuning range (VCO of SSPLL 206 has a second tuning range), but does not explicitly disclose wherein the second tuning range fully encompasses and is wider than the first tuning range.
However, Garlepp discloses, in figure 1 & 3, wherein the second tuning range fully encompasses and is wider than the first tuning range (Para [0024] & [0026], “VCO 324 has a 2.5 GHz center frequency, a Q of about three to ten, and a tuning range of about five percent…VCO 350 operaties at either 2.5 GHz or 3.125 GHz, exhibiting a tuning range of about 25%”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the tuning ranges of Garlepp in the cascaded PLL system of Wang and Hossain, to achieve the benefit of implementing a low-Q oscillator that exhibits a wide tuning range to support a number of high-speed transmit and receive data rates (Garlepp, Para [0017]).
Regarding claim 11, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, and Wang continues to disclose, in figure 2 & 3, wherein the first stage comprises a first voltage-controlled oscillator (VCO) having a first tuning range (Para [0039], “PLL 202 operates at relatively low frequency. Also, because the IF value is not constrained by any noise-based optimization, it can be selected based on a millimeter wavelength VCO tuning range”), but does not explicitly disclose wherein a quality factor (Q) of an LC tank in the first VCO is optimized with respect to the first tuning range.
However, Garlepp discloses, in figure 1 & 3, wherein a quality factor (Q) of an LC tank in the first VCO is optimized with respect to the first tuning range (Para [0024], “VCO 324 is a high-Q oscillator that may be based upon an LC tank circuit (not shown), and thus does not introduce considerable phase noise. VCO 324 has a 2.5 GHz center frequency, a Q of about three to ten, and a tuning range of about five percent. By combining a narrow loop bandwidth with a high-Q VCO, PLL 305 produces a relatively "clean" 625 MHz intermediate clock IRClk.”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the optimized quality factor of Garlepp in the VCO of Wang and Hossain, to achieve the benefit of minimizing VCO noise (Garlepp, Para [0024]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Hossain as applied to claims 1-3 & 12 above, and further in view of Doi (US 2009/0009223 A1).
Regarding claim 6, Wang in view of Hossain disclose the cascaded PLL system according to claim 1, but do not explicitly disclose wherein the first stage comprises an alternating current (AC)-coupled charge pump (ACCP) and a loop filter, wherein the ACCP is configured to isolate an output of the ACCP from the loop filter.
However, Doi discloses, in figures 1 & 17B, wherein the first stage comprises an alternating current (AC)-coupled charge pump (ACCP) and a loop filter (AC-coupled charge pump as disclosed in figure 17B and loop filter 28), wherein the ACCP is configured to isolate an output of the ACCP from the loop filter (AC-coupling capacitors C21-C23 isolate an output of the charge pump from the loop filter).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the AC-coupled charge pump of Doi in the first stage of Wang and Hossain, to achieve the benefit of more accurately adjusting a control voltage for the oscillator of the PLL (Doi, Para [0129]).
Regarding claim 7, the combination of Wang, Hossain, and Doi disclose the cascaded PLL system according to claim 6, and Doi continues to disclose, in figures 1 & 17B, wherein the ACCP comprises:
an output (output of charge pump 71); and
an AC-coupling capacitor configured to isolate the output from the loop filter (any of AC-coupled capacitors C21-C23).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Hossain as applied to claims 1-3 & 12 above, and further in view of Doi, and even further in view of Bhat et al. (US 11,398,827 B1), hereinafter Bhat.
Regarding claim 13, Wang in view of Hossain discloses the cascaded PLL system according to claim 1, and Wang continues to disclose, in figure 3, wherein the first stage comprises:
a first phase detector configured to receive a reference signal (PFD receiving a reference signal);
a first voltage-controlled oscillator (VCO) coupled to the loop filter (Ring VCO coupled to the loop filter LPF), but does not explicitly disclose an alternating current (AC)-coupled charge pump (ACCP) coupled to the phase detector;
a first loop filter coupled to the ACCP; and
a first buffer coupled to the first VCO and the first phase detector.
However, Doi discloses, in figures 1 & 17B, wherein the first stage comprises an alternating current (AC)-coupled charge pump (ACCP) coupled to the phase detector (AC-coupled charge pump as disclosed in figure 17B and loop filter 28 coupled to phase detector 24); and
a first loop filter coupled to the ACCP (loop filter 28 coupled to the AC-coupled charge pump 27/71).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the AC-coupled charge pump of Doi in the first stage of Wang and Hossain, to achieve the benefit of more accurately adjusting a control voltage for the oscillator of the PLL (Doi, Para [0129]).
In combination, Wang, Hossain, and Doi do not explicitly disclose a first buffer coupled to the first VCO and the first phase detector.
However, Bhat discloses, in figure 2, a first buffer coupled to the first VCO and the first phase detector (buffer 208A coupled to VCO 112A and phase detector 108A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the buffer of Bhat in the first stage of Wang, Hossain, and Doi, to achieve the benefit of delaying the oscillating signal from the VCO to avoid loading of the VCO by the phase detector (Bhat, Col. 5, Lines 14-18).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, Hossain, Doi, and Bhat as applied to claim 13 above, and further in view of Martin.
Regarding claim 14, the combination of Wang, Hossain, Doi, and Bhat disclose the cascaded PLL system according to claim 13, and Bhat continues to disclose, in figure 2, wherein the second stage comprises:
a reference buffer coupled to the first VCO (buffer 212 coupled to VCO 112A);
a second phase detector coupled to the reference buffer (second phase detector 108B coupled to buffer 212);
a second buffer coupled to the second VCO and to the second phase detector (buffer 208B coupled to VCO 112B and phase detector 108B), but does not explicitly disclose a second voltage-controlled oscillator (VCO) coupled to the phase detector via a first path and a second path, wherein the first path comprises a passive loop filter and the second path comprises a charge pump and a loop filter;
However, Martin discloses, in figure 5, a second voltage-controlled oscillator (VCO) coupled to the phase detector via a first path and a second path (VCO 525 coupled to the phase detector 410 via path 420/430 and 450/460), wherein the first path comprises a passive loop filter (passive filter 430) and the second path comprises a charge pump and a loop filter (charge pump 450 and loop filter 460);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dual-path loop of Martin in the second stage of Wang, Hossain, Doi, and Bhat to achieve the benefit of allowing the proportional path to have a relatively large current and therefore lower impedance in its passive filter components, resulting in reduced noise in the signal and improved jitter performance (Martin, Col. 7, Lines 7-27).
Allowable Subject Matter
Claims 8-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
Regarding claim 15, Doi discloses, in figures 1 & 17B, an alternating current (AC)-coupled charge pump (ACCP), comprising:
an output (output of the AC-coupled charge pump 27/71); and
an AC-coupling capacitor configured to isolate the output from a loop filter (any of AC-coupled capacitors C21-C23).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
a level alignment loop disposed between the AC-coupling capacitor and the loop filter, the level alignment loop comprising a unit-gain amplifier configured to align a direct current (DC) voltage level of the loop filter with a respective plate of the AC-coupling capacitor.
Regarding claim 18, Doi discloses, in figures 1 & 17B, an alternating current (AC)-coupled charge pump (ACCP), comprising:
an output (output of the AC-coupled charge pump 27/71); and
an AC-coupling capacitor configured to isolate the output from a loop filter (any of AC-coupled capacitors C21-C23).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
a dummy charge pump disposed between the output and the AC-coupling capacitor configured to maintain a preset voltage level.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zeinolabedinzadeh et al. (US 2025/0260408 A1) [Figure 1. Discloses a phase noise cancellation technique to reduce phase noise and improve timing stability in a variety of electronic devices. The system and method include two phase locked loops (PLLs) in a cascaded configuration. The second PLL is used as a buffer to collect the replicated correlated phase noise which is then used in a feedback circuit to cancel out the original phase noise on the first PLL.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
