DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9, 11-17, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent Nos. 12315409 and 11763716 in view of Won et al. (hereinafter Won – US Doc. No. 20190006431). Please see the chart below for claim correspondence.
19/188952
USPN12315409
USPN 11763716
1
1
1
2
2
2
3
3
2
4
4
-
5
5
-
6
6
3
7
7
-
8
8
-
9
9
-
10
-
-
11
12
-
12
13
4
13
14
7
14
15
8
15
16
-
16
17
-
17
18
-
18
-
-
19
20
10
The claims as shown above all recite similar features. It would have been obvious to one of ordinary skill in the art to use the claimed features of the reference application/patent to arrive at the instant claims, yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement. Please see an example of claim language correspondence below.
18/449635
USPN 12315409
1. A display panel, comprising: a substrate including a display area and another display area adjacent to the display area, the display area and the another display area including different numbers of subpixels per unit area from each other, and the display area having a transmissive area and a non-transmissive area adjacent to the transmissive area;
1. A display panel, comprising: a substrate including a display area and another display area adjacent to the display area, the display area and the another display area including different numbers of subpixels per unit area from each other, and the display area having a transmissive area and a non-transmissive area adjacent to the transmissive area;
a transistor on the substrate;
a transistor layer over the substrate;
a light emitting element on the transistor, the light emitting element including a first electrode and a second electrode;
a light emitting element layer on the transistor layer and including at least one light emitting element including a first electrode, a second electrode and a light emitting layer between the first electrode and the second electrode; and
an encapsulating element on the light emitting element;
an encapsulating element layer on the light emitting element layer,
a touch sensor layer on the encapsulating element; and
a touch sensor disposed in the touch sensor layer,
wherein, in the transmissive area of the display area, the encapsulating element does not overlap with the first electrode and the second electrode of the light emitting element,
wherein, in the transmissive area of the display area, the encapsulating element layer does not overlap with the first electrode and the second electrode of the light emitting element in a plan view.
and wherein the touch sensor layer includes a touch buffer layer and a touch insulating layer.
Neither of USPNs 12315409 or 11763716 recite the touch sensor layer on the encapsulating element or a touch sensor layer or that the touch sensor layer includes a touch buffer layer and a touch insulating layer.
The prior art of Won discloses a display (Figure 2) including a substrate (Figure 3, element 111), transistors (layer 10), and an encapsulating element (30) wherein the display further comprises a touch sensor layer (40) on the encapsulating element (30) wherein the touch sensor layer comprises touch sensors (see paragraphs 0057) and wherein the touch sensor layer includes a touch buffer layer and a touch insulating layer (see paragraph 0093).
It would have been obvious to combine the display panel as discussed in USPNs 12315409 or 11763716 with the display panel including a touch sensing layer as disclosed by Won, the combination yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement and would allow for user touch input on the display.
The rest of the claims listed above correspond in a similar manner as discussed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (hereinafter Ko – US Doc. No. 20220028949) in view of Won et al. (hereinafter Won – US Doc. No. 20190006431).
Regarding claim 1, Ko discloses a display panel, comprising:
a substrate (Figure 8, element 111) including a display area (Figure 12, element 100A1a/100A3a) and another display area adjacent to the display area (100A2a), the display area and the another display area including different numbers of subpixels per unit area from each other (as detailed in paragraph 0220), and the display area having a transmissive area and a non-transmissive area adjacent to the transmissive area (as discussed in paragraph 0171);
a transistor on the substrate (Figure 8, element 112);
a light emitting element (100A2P) on the transistor, the light emitting element including a first electrode (CE) and a second electrode (AE_2);
an encapsulating element on the light emitting element (60);
wherein, in the transmissive area of the display area, the encapsulating element does not overlap with the first electrode and the second electrode of the light emitting element (as shown in Figure 8 – note that the encapsulation layer 60 does not overlap with the first electrode CE and the second electrode AE_2 within the light emitting element 100PE_2). Although Ko discloses that the display panel can accept outside touch input (see paragraph 0067), Ko is silent on the implementation of the touch input sensing.
The prior art of Won discloses a display (Figure 2) including a substrate (Figure 3, element 111), transistors (layer 10), and an encapsulating element (30) wherein the display further comprises a touch sensor layer (40) on the encapsulating element (30), and the touch sensor layer comprises touch sensors (see paragraphs 0057), and wherein the touch sensor layer includes a touch buffer layer and a touch insulating layer (see paragraph 0093).
It would have been obvious to combine the display panel as disclosed by Ko with the display panel including a touch sensing layer as disclosed by Won, the combination yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement and would allow for user touch input on the display.
Regarding claim 2, the combination of Ko and Won discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above. Ko further discloses that the substrate includes an active area and a non-active area, wherein the display area and the another display area are in the active area (Figure 12, elements 100A1a/100A3a and 100A2a – note that both are within the active area 100A),
and wherein the display area includes a first display area (100A1a) and a second display area (100A3a).
Regarding claim 3, the combination of Ko and Won discloses all of the limitations of claim 2 as discussed in the claim 2 rejection above. Ko further discloses that the second display area is located at a boundary between the non-active area and the active area (see Figure 12 – note that 100A3a is within the active area 100Aa and next to 100N).
Regarding claim 4, the combination of Ko and Won discloses all of the limitations of claim 2 as discussed in the claim 2 rejection above. Ko further discloses that the first display area includes a pixel area and a wiring area, and wherein one of the first electrode and the second electrode serves as a common electrode and does not overlap the transmissive area (see paragraph 0161)
Regarding claim 5, the combination of Ko and Won discloses all of the limitations of claim 4 as discussed in the claim 4 rejection above. Ko further discloses that the common electrode is over substantially all of the second display area and the another display area (see paragraphs 0161-0162).
Regarding claim 6, the combination of Ko and Won discloses all of the limitations of claim 2 as discussed in the claim 2 rejection above. Ko further discloses that the substrate comprises a bezel area surrounding the first display area (Figure 12, element 100N), and
wherein the transistor is in the bezel area and includes a display line for applying a signal to the second display area (see Figures 7 and 8, element 100N).
Regarding claim 7, the combination of Ko and Won discloses all of the limitations of claim 6 as discussed in the claim 6 rejection above. Ko further discloses that the display line includes a data line (see paragraph 0114).
Regarding claim 8, the combination of Ko and Won discloses all of the limitations of claim 2 as discussed in the claim 2 rejection above. Ko further discloses a light-receiving device disposed in the first display area (see paragraph 0181 – note that the light receiving device is a camera).
Regarding claim 9, the combination of Ko and Won discloses all of the limitations of claim 8 as discussed in the claim 8 rejection above. Ko further discloses that the light-receiving device overlaps a part of the transmissive area of the display area (see paragraph 0181; see also Figure 12).
Regarding claim 10, the combination of Ko and Won discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above. Won further discloses a protective layer on the touch sensor layer (Figure 3, element 112).
Regarding claim 11, the combination of Ko and Won discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above. Ko further discloses at least one signal line on the transistor in the non-transmissive area of the display area (see Figures 7 and 8 – note elements CL which can be driving lines).
Regarding claim 12, the combination of Ko and Won discloses all of the limitations of claim 11 as discussed in the claim 11 rejection above. Ko further discloses that the at least one signal line includes at least one of one or more data lines, one or more gate lines, or one or more driving voltage lines (see Figures 7 and 8 – note elements CL which can be driving lines).
Regarding claim 13, Ko discloses a display device, comprising:
a display panel (Figure 1, element 1000A); and
a control circuit operatively coupled to the display panel (see paragraph 0061),
wherein the display panel includes:
a substrate (Figure 8, element 111) including a display area (Figure 12, element 100A1a/100A3a) and another display area adjacent to the display area (100A2a), the display area and the another display area including different numbers of subpixels per unit area from each other (as detailed in paragraph 0220), and the display area having a transmissive area and a non-transmissive area adjacent to the transmissive area (as discussed in paragraph 0171);
a transistor on the substrate (Figure 8, element 112);
a light emitting element (100A2P) on the transistor, the light emitting element including a first electrode (CE) and a second electrode (AE_2);
an encapsulating element on the light emitting element (60);
wherein, in the transmissive area of the display area, the encapsulating element does not overlap with the first electrode and the second electrode of the light emitting element (as shown in Figure 8 – note that the encapsulation layer 60 does not overlap with the first electrode CE and the second electrode AE_2 within the light emitting element 100PE_2). Although Ko discloses that the display panel can accept outside touch input (see paragraph 0067), Ko is silent on the implementation of the touch input sensing.
The prior art of Won discloses a display (Figure 2) including a substrate (Figure 3, element 111), transistors (layer 10), and an encapsulating element (30) wherein the display further comprises a touch sensor layer (40) on the encapsulating element (30), and the touch sensor layer comprises touch sensors (see paragraphs 0057), and wherein the touch sensor layer includes a touch buffer layer and a touch insulating layer (see paragraph 0093).
It would have been obvious to combine the display panel as disclosed by Ko with the display panel including a touch sensing layer as disclosed by Won, the combination yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement and would allow for user touch input on the display.
Regarding claim 14, the combination of Ko and Won discloses all of the limitations of claim 13 as discussed in the claim 13 rejection above. Ko further discloses that the substrate includes an active area and a non-active area, wherein the display area and the another display area are in the active area (Figure 12, elements 100A1a/100A3a and 100A2a – note that both are within the active area 100A),
wherein the display area includes a first display area (100A1a) and a second display area (100A3a), and
wherein the second display area is at a boundary between the non-active area and the active area (see Figure 12 – note that 100A3a is within the active area 100Aa and next to 100N).
Regarding claim 15, the combination of Ko and Won discloses all of the limitations of claim 14 as discussed in the claim 14 rejection above. Ko further discloses that one of the first electrode and the second electrode serves as a common electrode and does not overlap the transmissive area (see paragraph 0161), and
wherein the common electrode is over substantially all of the second display area and the another display area (see paragraphs 0161-0162).
Regarding claim 16, the combination of Ko and Won discloses all of the limitations of claim 14 as discussed in the claim 14 rejection above. Ko further discloses that the substrate comprises a bezel area surrounding the first display area (Figure 12, element 100N), and
wherein the transistor is in the bezel area and includes a display line for applying a signal to the second display area (see Figures 7 and 8, element 100N).
Regarding claim 17, the combination of Ko and Won discloses all of the limitations of claim 13 as discussed in the claim 13 rejection above. Ko further discloses a light-receiving device disposed in the first display area (see paragraph 0181 – note that the light receiving device is a camera),
wherein the light-receiving device overlaps a part of the transmissive area of the display area (see paragraph 0181; see also Figure 12).
Regarding claim 18, the combination of Ko and Won discloses all of the limitations of claim 13 as discussed in the claim 13 rejection above. Won further discloses a protective layer on the touch sensor layer (Figure 3, element 112).
Regarding claim 19, the combination of Ko and Won discloses all of the limitations of claim 13 as discussed in the claim 13 rejection above. Ko further discloses at least one signal line disposed over the transistor in the non-transmissive area of the display area (see Figures 7 and 8 – note elements CL which can be driving lines),
wherein the at least one signal line includes at least one of one or more data lines, one or more gate lines, or one or more driving voltage line (see Figures 7 and 8 – note elements CL which can be driving lines).
Conclusion
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/ADAM R. GIESY/ Primary Examiner, Art Unit 2622