DETAILED ACTION
This Office Action is in response to Applicants’ Application filed on April 24, 2025. Claims 1-20 are pending and presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 29, 2025 has been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the status of the related applications in paragraph 0001 needs to be updated.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,301,713. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the present application are broader in scope and thus encompass the subject matter already claimed.
U.S. Application 19/189,083
1. A device, comprising:
memory having a device secret configured during manufacture of the memory, the memory configured to provide a storage space;
an interface operable for a host system to communicate to the device a command to access the storage space; and
a circuit configured to manage, based on the device secret, a proof of space plot stored in the storage space and control, based on the device secret, access to the storage space over the interface.
2. The device of claim 1, wherein the circuit is further configured to: generate, based on the device secret, a cryptographic key pair including a private key and a public key.
3. The device of claim 2, wherein the circuit is further configured to: determine an identification of the proof of space plot based at least in part on the public key.
4. The device of claim 3, wherein the proof of space plot includes a plurality of look up tables.
5. The device of claim 4, wherein the circuit is further configured to: generate, based on the device secret, a secret key; and generate a verification code of identity data of the device using the device secret.
6. The device of claim 5, wherein the identity data includes a unique identification of the device.
7. The device of claim 4, wherein the circuit is further configured to: generate, based on the device secret, an access control key; and validate the command received from outside of the device using the access control key before execution of the command.
8. The device of claim 7, wherein the storage space includes a secure region and a non-secure region; and the device is configured to validate the command in response to the command being configured to access the secure region.
9. A method, comprising:
providing, by a device having a device secret configured during manufacture of memory of the device, a storage space;
receiving, in an interface of the device and from a host system, a command to access the storage space;
controlling, by the device based on the device secret, access to the storage space via the command; and
managing, by the device based on the device secret, a proof of space plot stored in the storage space.
10. The method of claim 9, further comprising: generate, by the device based on the device secret, a cryptographic key pair including a private key and a public key.
11. The method of claim 10, further comprising: determining, by the device, an identification of the proof of space plot based at least in part on the public key.
12. The method of claim 11, wherein the proof of space plot includes a plurality of look up tables.
13. The method of claim 12, further comprising: generating, by the device based on the device secret, a secret key; and generating, by the device, a verification code of identity data of the device using the device secret.
14. The method of claim 13, wherein the identity data includes a unique identification of the device.
15. The method of claim 12, further comprising:
generating, by the device based on the device secret, an access control key; and validating, by the device, the command received from outside of the device using the access control key before execution of the command.
16. An integrated circuit memory device, comprising:
a non-secure memory region;
a secure memory region;
a unique device secret configured in the integrated circuit memory device during manufacture of the integrated circuit memory device; and a controller;
wherein the integrated circuit memory device configured to store cryptographic keys in the secure memory region, control access to the secure memory region based on the unique device secret, and manage a proof of space plot in the integrated circuit memory device based at least in part on the unique device secret.
17. The integrated circuit memory device of claim 16, wherein the controller includes a cryptographic engine configured to generate the cryptographic keys based on the unique device secret.
18. The integrated circuit memory device of claim 17, wherein the controller further includes an access controller configured to control access to the secure memory region using an access control key generated based on the unique device secret.
19. The integrated circuit memory device of claim 18, wherein the controller is further configured to generate data representative of an identity of the integrated circuit memory device based on the unique device secret.
20. The integrated circuit memory device of claim 19, wherein the data includes a message showing a unique identification and a verification code generated using a secret key derived from the unique device secret.
U.S. Pat. No. 12,301,713
1. An apparatus, comprising: a storage medium including a memory device configured with a device secret during manufacture of the memory device; a host interface configured to communicate with a host system to provide the host system with data storage services using a storage capacity of the storage medium; and a logic circuit configured to: generate, based on the device secret, a cryptographic key pair including a private key and a public key; determine an identification of a proof of space plot, wherein the identification is based at least in part on the public key; and generate, in the storage medium, a plurality of look up tables of the proof of space plot having the identification.
2. The apparatus of claim 1, further comprising: a network interface operable to communicate, over a computer network, with a security server to initiate generation of the proof of space plot.
3. The apparatus of claim 2, wherein the security server is configured to store a plurality of cryptographic keys, including a first cryptographic key representative of an identity of the memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots.
4. The apparatus of claim 3, wherein the identification of the proof of space plot is further based on the third cryptographic key.
5. The apparatus of claim 4, wherein the logic circuit is configured to request, via the network interface, the security server to generate the third cryptographic key representative of the pool.
6. The apparatus of claim 5, wherein the logic circuit is further configured to generate a fourth cryptographic key representative of the proof of space plot.
7. The apparatus of claim 6, wherein the device secret is unique for the memory device among memory devices manufactured in a facility.
8. The apparatus of claim 7, wherein the fourth cryptographic key is generated based at least in part on the device secret.
9. The apparatus of claim 7, wherein the third cryptographic key is generated based at least in part on the device secret.
10. The apparatus of claim 7, wherein the fourth cryptographic key is a private key in a first asymmetric cryptographic key pair; and the third cryptographic key is a private key in a second asymmetric cryptographic key pair; and the identification of the proof of space plot is based on public keys in the first asymmetric cryptographic key pair and the second asymmetric cryptographic key pair.
11. A method, comprising: storing, in a memory device of an apparatus, a device secret configured in the memory device during manufacture of the memory device; communicating with, via a host interface of the apparatus, a host system to provide the host system with data storage services using a storage capacity of the apparatus; and generating, by the apparatus based on the device secret, a cryptographic key pair including a private key and a public key; determining, by the apparatus, an identification of a proof of space plot, wherein the identification is based at least in part on the public key; and generating, in a storage medium of the apparatus, a plurality of look up tables of the proof of space plot having the identification.
12. The method of claim 11, further comprising: communicating, via a network interface of the apparatus and over a computer network, with a security server to initiate generation of the proof of space plot.
13. The method of claim 12, wherein the security server is configured to store a plurality of cryptographic keys, including a first cryptographic key representative of an identity of the memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots.
14. The method of claim 13, wherein the identification of the proof of space plot is further based on the third cryptographic key.
15. The method of claim 14, further comprising: requesting, by the apparatus via the network interface, the security server to generate the third cryptographic key representative of the pool.
16. The method of claim 15, further comprising: generating, by the apparatus, a fourth cryptographic key representative of the proof of space plot.
17. The method of claim 16, wherein the fourth cryptographic key is a private key in a first asymmetric cryptographic key pair; and the third cryptographic key is a private key in a second asymmetric cryptographic key pair; and the identification of the proof of space plot is based on public keys in the first asymmetric cryptographic key pair and the second asymmetric cryptographic key pair.
18. A non-transitory computer storage medium storing instructions which, when executed by an apparatus, cause the apparatus to perform a method, comprising: communicating with, via a host interface of the apparatus, a host system to provide the host system with data storage services using a storage capacity of the apparatus; and generating, by the apparatus based on a device secret configured in a memory device during manufacture of the memory device, a cryptographic key pair including a private key and a public key; determining, by the apparatus, an identification of a proof of space plot, wherein the identification is based at least in part on the public key; and generating, in the storage capacity of the apparatus, a plurality of look up tables of the proof of space plot having the identification.
19. The non-transitory computer storage medium of claim 18, wherein the method further comprises: communicating, via a network interface of the apparatus and over a computer network, with a security server to initiate generation of the proof of space plot; wherein the security server is configured to store a plurality of cryptographic keys, including a first cryptographic key representative of an identity of the memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots.
20. The non-transitory computer storage medium of claim 19, wherein the cryptographic key pair is a first asymmetric cryptographic key pair; the third cryptographic key is a private key in a second asymmetric cryptographic key pair; and the identification is further based on a public key in the second asymmetric cryptographic key pair.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LASHONDA T JACOBS-BURTON whose telephone number is (571)272-4004. The examiner can normally be reached M-F 8:30 am - 5:00 pm.
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/LASHONDA JACOBS-BURTON/Primary Examiner, Art Unit 2457
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July 23, 2026
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