Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Continuation filed on 4/25/2025.
Claims 1-20 are pending for this examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/14/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 2005/0149648), herein referred to as Chiang ‘648, in view of Elliott et al. (US 2006/0106997), herein referred to as Elliott ‘997.
Referring to claim 1, Chiang ‘648 teaches a method (see Abstract) comprising:
arbitrating (see Fig. 2, arbitrator 229) between two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225) that can seek access to a memory (see Fig. 2, first IO device 241, second IO device 243, third IO device 245; also see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145); and
enabling one or more communication paths between the memory and a first storage system controller (see Paragraph 0023, where arbitrator 229 enables one of the controller to access one of the IO devices through a corresponding enable pine CE1, CE2, CE4, CE4), of the two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225), that is determined to have access to the memory (see Paragraph 0023; see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145),
wherein enabling the one or more communication paths comprises activating one or more components that permit communication between the first storage system controller and the memory (see Paragraph 0023, where arbitrator 229 enables one of the IO devices to be accessed through a corresponding enable pin, i.e. activating the corresponding enable pin and corresponding IO devices / memory card thereby permitting access), and
wherein one or more other components that could permit communication between the memory and a second storage system controller of the two or more storage system controllers are deactivated (see Paragraph 0023, where arbitrator 229 disables the other controller, i.e. deactivated).
However, Chiang ‘648 does not teach the memory being a single-ported storage device.
Elliott ‘997 teaches a system with multiple hosts connected to a single ported storage drive (see Abstract; see Fig. 1, hosts 12 and 14, storage drive 18; see Paragraphs 0012-0013).
Chiang ‘648 and Elliott ‘997 apply as analogous prior arts as both pertain to the same field of endeavor of having multiple requestors, i.e. hosts or controller, trying to access storage / memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang ‘648 system as set forth above to have the memory card devices be single-ported memory devices, as taught by Elliott ‘997, as a person of ordinary skill in the art would recognize and be motivated to utilize single ported storage devices as single-ported storage devices provide for higher security, lower hardware costs, and simpler management compared with multi-port storage devices as all data traffic has to go through a singular interface path and controller.
As to claim 2, Chiang ‘648 teaches the method of claim 1, wherein the arbitration is performed by a software-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element, which would require software instructions to control, i.e. arbitration performed via software controller arbiter).
As to claim 3, Chiang ‘648 teaches the method of claim 1, wherein the arbitration is performed by a hardware-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element).
As to claim 7, Chiang ‘648 teaches the method of claim 1, wherein the one or more components that are activated or deactivated comprise routing elements that control physical or logical paths between the storage system controllers and the single-ported storage device (see Fig. 2, multiplexer 227 which selects one controller of the multiple controllers, and CE1-4, where only one enable signal is needed to enable communications with the corresponding IO device / memory device 241, 243, 245).
Referring to claim 8, Chiang ‘648 teaches the a storage system (see the system of Fig. 2, wherein IO devices can be memory card devices, see Fig. 1) comprising one or more storage devices (see Fig. 2, first IO device 241, second IO device 243, third IO device 245; also see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145), the storage system to carry out the steps of:
arbitrating (see Fig. 2, arbitrator 229) between two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225) that can seek access to a memory (see Fig. 2, first IO device 241, second IO device 243, third IO device 245; also see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145); and
enabling one or more communication paths between the memory and a first storage system controller (see Paragraph 0023, where arbitrator 229 enables one of the controller to access one of the IO devices through a corresponding enable pine CE1, CE2, CE4, CE4), of the two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225), that is determined to have access to the memory (see Paragraph 0023; see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145),
wherein enabling the one or more communication paths comprises activating one or more components that permit communication between the first storage system controller and the memory (see Paragraph 0023, where arbitrator 229 enables one of the IO devices to be accessed through a corresponding enable pin, i.e. activating the corresponding enable pin and corresponding IO devices / memory card thereby permitting access), and
wherein one or more other components that could permit communication between the memory and a second storage system controller of the two or more storage system controllers are deactivated (see Paragraph 0023, where arbitrator 229 disables the other controller, i.e. deactivated).
However, Chiang ‘648 does not teach the memory being a single-ported storage device, or the system having one or more central processing units (CPUs), a computer memory operatively coupled to a computer processor, the computer memory having disposed within it computer program instructions.
Elliott ‘997 teaches a system with multiple hosts connected to a single ported storage drive (see Abstract; see Fig. 1, hosts 12 and 14, storage drive 18; see Paragraphs 0012-0013). Examiner points out that a standard computer in the art by definition would include at least one processor, memory coupled the processor, where computer instructions stored on memory can be executed by the processor such as BIOS.
Chiang ‘648 and Elliott ‘997 apply as analogous prior arts as both pertain to the same field of endeavor of having multiple requestors, i.e. hosts or controller, trying to access storage / memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang ‘648 system as set forth above to have the memory card devices be single-ported memory devices, as taught by Elliott ‘997, where the system includes at least one processor, memory coupled to the processor, and computer instruction stored within the memory that are executed by the processor, which are inherent components by definition for any computer, as a person of ordinary skill in the art would recognize and be motivated to utilize single ported storage devices as single-ported storage devices provide for higher security, lower hardware costs, and simpler management compared with multi-port storage devices as all data traffic has to go through a singular interface path and controller.
As to claim 9, Chiang ‘648 teaches the storage system of claim 8, wherein the computer program instructions that, when executed, further cause the storage system to carry out the step of: determining that the first storage system controller has gained exclusive access to the storage device using a software-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element, which would require software instructions to control, i.e. arbitration performed via software controller arbiter).
As to claim 10, Chiang ‘648 teaches the storage system of claim 8, wherein the computer program instructions that, when executed, further cause the storage system to carry out the step of: determining that the first storage system controller has gained exclusive access to the single-ported storage device using a hardware-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element).
As to claim 14, Chiang ‘648 teaches the storage system of claim 8, wherein the one or more components that are activated or deactivated comprise routing elements that control physical or logical paths between the storage system controllers and the single-ported storage device (see Fig. 2, multiplexer 227 which selects one controller of the multiple controllers, and CE1-4, where only one enable signal is needed to enable communications with the corresponding IO device / memory device 241, 243, 245).
Referring to claim 15, Chiang ‘648 teaches a computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer (see the system of Fig. 2, wherein IO devices can be memory card devices, see Fig. 1) to carry out the steps of:
arbitrating (see Fig. 2, arbitrator 229) between two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225) that can seek access to a memory (see Fig. 2, first IO device 241, second IO device 243, third IO device 245; also see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145); and
enabling one or more communication paths between the memory and a first storage system controller (see Paragraph 0023, where arbitrator 229 enables one of the controller to access one of the IO devices through a corresponding enable pine CE1, CE2, CE4, CE4), of the two or more storage system controllers (see Fig. 2, first controller 221, second controller 223, third controller 225), that is determined to have access to the memory (see Paragraph 0023; see Fig. 1, wherein the IO devices can be memory card devices 141, 143, 145),
wherein enabling the one or more communication paths comprises activating one or more components that permit communication between the first storage system controller and the memory (see Paragraph 0023, where arbitrator 229 enables one of the IO devices to be accessed through a corresponding enable pin, i.e. activating the corresponding enable pin and corresponding IO devices / memory card thereby permitting access), and
wherein one or more other components that could permit communication between the memory and a second storage system controller of the two or more storage system controllers are deactivated (see Paragraph 0023, where arbitrator 229 disables the other controller, i.e. deactivated).
However, Chiang ‘648 does not teach the memory being a single-ported storage device, or the computer having a computer program product disposed upon a non-transitory computer readable storage medium comprising computer program instructions that are executed by the computer.
Elliott ‘997 teaches a system with multiple hosts connected to a single ported storage drive (see Abstract; see Fig. 1, hosts 12 and 14, storage drive 18; see Paragraphs 0012-0013). Examiner points out that a standard computer in the art by definition would include at least one processor, memory coupled the processor, where computer instructions stored on memory can be executed by the processor such as BIOS.
Chiang ‘648 and Elliott ‘997 apply as analogous prior arts as both pertain to the same field of endeavor of having multiple requestors, i.e. hosts or controller, trying to access storage / memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang ‘648 system as set forth above to have the memory card devices be single-ported memory devices, as taught by Elliott ‘997, where the system includes at least one processor, memory coupled to the processor, and computer instruction stored within the memory that are executed by the processor, which are inherent components by definition for any computer, as a person of ordinary skill in the art would recognize and be motivated to utilize single ported storage devices as single-ported storage devices provide for higher security, lower hardware costs, and simpler management compared with multi-port storage devices as all data traffic has to go through a singular interface path and controller.
As to claim 16, Chiang ‘648 teaches the computer program product of claim 15, wherein the computer program instructions that, when executed, further cause the computer to carry out the step of: determining that the first storage system controller has gained exclusive access to the storage device using a software-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element, which would require software instructions to control, i.e. arbitration performed via software controller arbiter).
As to claim 17, Chiang ‘648 teaches the computer program product of claim 15, wherein the computer program instructions that, when executed, further cause the computer to carry out the step of: determining that the first storage system controller has gained exclusive access to the single-ported storage device using a hardware-based arbiter device (see Fig. 2, arbitrator 229, which is a hardware element).
Allowable Subject Matter
Claims 4-6, 11-13, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 4, 11, and 18, Examiner finds that prior art does not specifically teach the enabling the one or more communication paths comprises: identifying a first lane arrangement for data lanes of the first storage system controller and a second lane arrangement for data lanes of the single-ported storage device, wherein the first lane arrangement is different from the second lane arrangement; and enabling communication between the data lanes in the first lane arrangement and data lanes in the second lane arrangement.
As to claims 6, 13, and 20, Examiner finds that prior art does not specifically teach further comprising communicating reset signals from the first storage system controller to the single-ported storage device over a sideband interface.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ohara (US 6,286,070) teaches a shared memory system with two bus access controller and an arbitration circuit the arbitrate accesses to the shared memory.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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