Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/11/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12306773, 1-20 of U.S. Patent No. 11755504, 1-20 of U.S. Patent No. 10747689, 1-20 of U.S. Patent No. 10185672, claims 1-30 of U.S. Patent No. 9292464, claims 1-20 of U.S. Patent No. 9612984. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application and patents claim a plurality of routers forming a primary interconnection network, a plurality of interface units coupled together to form a secondary interconnection network, a plurality of processors coupled to the plurality of routers, and wherein each processor of the plurality of processors is coupled to a respective one of the plurality of interface units; and a bus controller coupled to a particular interface unit and a particular router each associated with a particular processor, wherein the bus controller is configured to communicate via the primary and secondary interconnection network.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-12, and 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Applicant’s Admitted Prior Art, hereafter referred to as AAPA.
Referring to claim 1, AAPA, as claimed, an apparatus (see Fig. 1), comprising: a bus controller coupled to at least one specified interface unit of a plurality of interface units (serial bus controller (SBC) unit linking local interface units, see para. [0006]), wherein each of the plurality of interface units is coupled to a respective processor of a plurality of processors and a respective router of a plurality of routers (each SBS interface unit is coupled to one PE, one SM, one SB input link, and one SB output link, see para. [0006] and Fig. 1), wherein the plurality of routers form a primary interconnection network (primary interconnection network (PIN), see paras. [0004] and [0005]), wherein the plurality of interface units are coupled together to form a secondary interconnection network (serial bus (SB), also referred to as secondary interconnection network (SIN), see para. [0005]), wherein the bus controller is configured to: send data to and receive data from the at least one specified interface unit (Each SBS unit was assigned a unique address value so that individual messages could be send to particular SBS units; each link between interface units carrying a data signal (SBDATA), see para. [0006]); arbitrate requests for access to the at least one specified interface unit (If two controllers attempt to initiate channels at the same time, then the SBC will arbitrate so that one gains access, see para. [0008]); and perform a comparison between messages received from each of two or more processors of the plurality of processors and perform a particular one of a plurality of actions based upon results of the comparison (compare the address in the message header. In the case of an address match, the SBS-IU may enter channel mode where subsequent messages are treated as possible commands until it receives a command to return to repeater mode. The SBS-IU may be configured to decode a set of commands from properly-encoded SB messages, see para. [0007]).
As to claim 2, AAPA also discloses to perform the particular one of the plurality of actions, the bus controller is further configured to send one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match (compare the address in the message header. In the case of an address match, the SBS-IU may enter channel mode where subsequent messages are treated as possible commands until it receives a command to return to repeater mode. The SBS-IU may be configured to decode a set of commands from properly-encoded SB messages, see para. [0007] and Fig. 1).
As to claim 3, AAPA also discloses an error handler unit (to prevent more than one controller at a time from gaining access, which may produce random mixing of commands and erroneous results, see para. [0008]).
As to claim 4, AAPA also discloses to perform the particular one of the plurality of actions, the bus controller is further configured to send a command to the error handler unit in response to a determination that the messages received from each of the two or more processors do not match (If there is no address match, the SBS-IU may pass the message on to the next SBS-IU in the chain…If an SB message is not properly encoded for one of the set of commands, then the SBS-IU ignores it, see paras. [0007], [0008] and Fig. 1; also note: to prevent more than one controller at a time from gaining access, which may produce random mixing of commands and erroneous results, see para. [0008]).
As to claim 5, AAPA also discloses the error handler unit is configured to report a tamper event in response to receiving the command from the bus controller (reset DMR, reset PE, reset I/O circuits, set security barriers, force PE break, disable PE participation, generate a return SB message, see para. [0007]; also note: to prevent more than one controller at a time from gaining access, which may produce random mixing of commands and erroneous results, see para. [0008]).
As to claim 6, AAPA also discloses a plurality of Input/Output (I/O) circuits, wherein the error handler unit is configured to disable the I/O circuits in response to receiving the command from the bus controller (reset DMR, reset PE, reset I/O circuits, set security barriers, force PE break, disable PE participation, see para. [0007]; also note: to prevent more than one controller at a time from gaining access, which may produce random mixing of commands and erroneous results, see para. [0008]).
Note claims 8 and 14 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 9 and 15 recite the corresponding limitations of claim 2. Therefore they are rejected based on the same reason accordingly.
Note claims 10 and 17 recite similar limitations of claim 4. Therefore they are rejected based on the same reason accordingly.
Note claims 11 and 18 recite the corresponding limitations of claim 5. Therefore they are rejected based on the same reason accordingly.
Note claims 12 and 19 recite the corresponding limitations of claim 6. Therefore they are rejected based on the same reason accordingly.
Note claim 16 recites the corresponding limitations of claim 3. Therefore it is rejected based on the same reason accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Diluoffo et al. (U.S. Publication No. 2008/0111579 A1), hereafter referred to as Diluoffo’579.
As to claim 7, AAPA does not explicitly teach comprising a plurality of fuses and configured to blow at least one fuse of the plurality of fuses in response to receiving a command.
Diluoffo’579 discloses a plurality of fuses and configured to blow at least one fuse of the plurality of fuses in response to receiving a command (anti-tamper fuses will blow when circuit is tampered with and decoy fuses cause incorrect data to propagate to logic element(s) when operation is attempted, see paras. [0023], [0025], and [0028]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify AAPA’s invention to comprise a plurality of fuses and configured to blow at least one fuse of the plurality of fuses in response to receiving a command, as taught by Diluoffo’579, in order to cause a circuit to malfunction guarding against reverse engineering and/or tampering (see para. [0006]).
Note claims 13 and 20 recite the corresponding limitations of claim 7. Therefore they are rejected based on the same reason accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Abts et al. (U.S. Patent No. 8,285,789 B2) discloses flattened butterfly processor interconnect network.
Mukherjee (U.S. Patent No. 7,649,845 B2) discloses handling hot spots in interconnection networks.
Kim et al. (U.S. Patent No. 8,228,930 B1) discloses interconnection network router arrangements.
Kim (U.S. Patent No. 6,304,568 B1) discloses interconnection network extendable bandwidth and transferring data therein.
Rankin et al. (U.S. Patent No. 7,930,464 B2) discloses scalable memory and I/O multiprocessor systems.
Pitts (U.S. Publication No. 2004/0100302 A1) discloses adaptive algorithm for electrical fuse programming.
Tu et al. (U.S. Publication No. 2002/0116664 A1) discloses method for machine check abort handling in a multiprocessing system.
Hsu et al. (U.S. Publication No. 2010/0225380 A1) discloses implementing tamper resistant integrated circuit chips.
Pedersen (U.S. Patent No. 8,736,299 B1) discloses setting security features of programmable logic devices.
Diluoffo et al. (U.S. Publication No. 2008/0111682 A1) discloses anti-tamper electronic circuitry using e-fuse technology.
Erlebacher et al. (U.S. Publication No. 2005/0224586 A1) discloses circuits associated with fusible elements for establishing and detecting of the states of those elements.
Watanabe (U.S. Publication No. 2002/0129184 A1) discloses effective bus utilization using bus arbiter.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TITUS WONG whose telephone number is (571)270-1627. The examiner can normally be reached Monday-Friday, 10am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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