Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/25/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, and 11-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by DODDI et al. (U.S. Publication No. 2025/0021504 A1), hereafter referred to as DODDI’504.
Referring to claim 1, DODDI’504, as claimed, an integrated circuit, comprising:
a first circuit die comprising a first die controller (first die 101 with module 103, see Fig. 1), a first TX repair control circuit (module 103 has main band transmitter 110 that is connected to transmit part 132 that includes redundant lines, see paras. [0025], [0026], [0028]-[0031] and Fig. 1; also note: sideband 136 has a transmit part each with a sideband data line and a sideband clock line, see para. [0028] and Fig. 1), and a first RX repair control circuit (module 103 has main band receiver 112 that is connected to receive part 134 includes redundant lines, see paras. [0025], [0026], [0028]-[0031] and Fig. 1; also note: sideband 136 has a transmit part each with a sideband data line and a sideband clock line, see para. [0028] and Fig. 1); a second circuit die comprising a second die controller (second die 102 with module 104, see Fig. 1), a second TX repair control circuit (module 104 has main band transmitter 122 that is connected to transmit part 132 that includes redundant lines, see paras. [0025], [0026], [0028]-[0031] and Fig. 1; also note: sideband 136 has a transmit part each with a sideband data line and a sideband clock line, see para. [0028] and Fig. 1), and a second RX repair control circuit (module 104 has main band receiver 120 that is connected to receive part 134 includes redundant lines, see paras. [0025], [0026], [0028]-[0031] and Fig. 1; also note: sideband 136 has a transmit part each with a sideband data line and a sideband clock line, see para. [0028] and Fig. 1); and an interconnect layer that electrically connects the first circuit die and the second circuit die (connection 100 has main band 130 and sideband 136, see Fig. 1 and paras. [0025] and [0028]), wherein: the first TX repair control circuit is configured to transmit a test pattern to the second RX repair control circuit via the interconnect layer; the second RX repair control circuit is configured to determine that a first interconnect in the interconnect layer has failed based on the test pattern received from the first TX repair control circuit; the second RX repair control circuit is configured to transmit a signature indicating that the first interconnect has failed to the second die controller; the first TX repair control circuit is configured to deactivate the first interconnect and to activate a second interconnect in the interconnect layer based on a first instruction received from the second die controller; and the second RX repair control circuit is configured to deactivate the first interconnect and to activate the second interconnect based on a second instruction received from the second die controller (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]).
As to claim 2, DODDI’504 also discloses the first TX repair control circuit is configured to deactivate the first interconnect and activate the second interconnect via a first multiplexer on the first circuit die; and the second RX repair control circuit is configured to deactivate the first interconnect and activate the second interconnect via a second multiplexer on the second circuit die (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; various hardware components that implement the operations, see paras. [0076]-[0078], [0089], [0096], and [0097]).
As to claim 3, DODDI’504 also discloses the second RX repair control circuit is configured to determine that the first interconnect has failed based on the test pattern received from the first TX repair control circuit by comparing the test pattern to an expected pattern (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; patterns and comparing, see paras. [0050], [0053], and [0057]).
As to claim 4, DODDI’504 also discloses the second RX repair control circuit is configured to synchronize the test pattern and the expected pattern by: comparing a portion of the test pattern to a portion of a first expected pattern to determine a number of differences between the portion of the test pattern and the portion of the first expected pattern; responsive to determining that the number of differences is below a threshold, using the first expected pattern as the expected pattern; and responsive to determining that the number of differences is above the threshold, using a second expected pattern as the expected pattern (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; patterns and comparing, see paras. [0050], [0053], and [0057]).
As to claim 5, DODDI’504 also discloses the second RX repair control circuit is configured to: generate the signature by capturing differences between the test pattern and the expected pattern (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; patterns and comparing, see paras. [0050], [0053], and [0057]) using sticky flip-flops; and store the signature in a shift register of the RX repair control circuit (shifting, see para. [0037]; also note: logs the detection result, see para. [0053]).
As to claim 6, DODDI’504 also discloses the second RX repair control circuit is configured to disconnect a clock signal from the second RX repair control circuit after the RX repair control circuit generates the signature (reset state and PHY retraining where data lines or clock lines may be trained, see paras. [0030], [0044], [0046], [0050], [0057], [0082] and Fig. 3).
As to claim 7, DODDI’504 also discloses the first TX repair control circuit is configured to transmit the test pattern to the second RX repair control circuit based on a third instruction received from a test access port (TAP) on the first circuit die (a command may be in a form of receiving a request through control interface 830 and data interface 832, see paras. [0078], [0079], [0086] and Fig. 8).
As to claim 9, DODDI’504 also discloses the first die controller does not receive any data indicative of failure of any of the interconnects from the second circuit die (proper operation, see paras. [0052], [0053]).
As to claim 11, DODDI’504 also discloses the second TX repair control circuit is configured to transmit a second test pattern (patterns and comparing, see paras. [0050], [0053], and [0057] to the first RX repair control circuit via the interconnect layer; the first RX repair control circuit is configured to determine that a third interconnect in the interconnect layer has failed based on the second test pattern received from the second TX repair control circuit; the first RX repair control circuit is configured to transmit a second signature indicating that the third interconnect has failed to the first die controller;
the second TX repair control circuit is configured to deactivate the third interconnect and to activate a fourth interconnect in the interconnect layer based on a fourth instruction received from the first die controller; and the first RX repair control circuit is configured to deactivate the third interconnect and activate the fourth interconnect based on a fifth instruction received from the first die controller (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]).
As to claim 12, DODDI’504 also discloses the first die controller does not receive any data indicative of failure of any of the interconnects from the second circuit die (proper operation, see paras. [0052], [0053]).
Note claims 13 and 16 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 14 and 18 recite similar limitations of claim 3. Therefore they are rejected based on the same reason accordingly.
Note claims 15 and 20 recite similar limitations of claim 5. Therefore they are rejected based on the same reason accordingly.
As to claim 17, DODDI’504 also discloses storing, in a non-volatile memory of the second circuit die, the signature indicating that the first interconnect has failed (logs the detection result, see para. [0053]).
As to claim 19, DODDI’504 also discloses generating, by the second circuit die, the signature indicating that the first interconnect has failed comprises comparing, by the second circuit die, the test pattern received from the first circuit die to an expected pattern (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; patterns and comparing, see paras. [0050], [0053], and [0057]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over DODDI’504 in view of Khurana et al. (U.S. Patent No. 11,379,644), hereafter referred to as Khurana’644.
As to claim 8, DODDI’504 also discloses the test access port on the first circuit die is configured to transmit the third instruction to the first TX repair control circuit (the repair main band state 414 is a training state of the main band data communications in which known patterns are transmitted on the data lines to test each data lane for proper operation. Each data lane is tested in both the transmit data line and the receive data line. Upon detecting a faulty data line in either direction through the repair main band state 414, then the data link width may be modified to exclude the faulty data line., see para. [0052] and Fig. 4; also note: either side may initiate repair or training and either side may initiate parameter, and configuration changes, etc., see para. [0026]; a command may be in a form of receiving a request through control interface 830 and data interface 832, see paras. [0078], [0079], [0086] and Fig. 8).
However, DODDI’504 does explicitly teach via a Segmented Instrument Access Network (SIAN) in accordance with Internal Joint Test Action Group (iJTAG) standards.
Khurana’644 discloses via a Segmented Instrument Access Network (SIAN) in accordance with Internal Joint Test Action Group (iJTAG) standards (test access port (TAP) coupled upstream from the SIB 138 provides an interface for external systems to provide stimuli to components of chip, see Col. 5, line 9 to Col. 6, line 45 and Figs. 1-4; also note: iJTAG standard, see Col. 1, lines 27-30).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify DODDI’504’s invention to comprise via a Segmented Instrument Access Network (SIAN) in accordance with Internal Joint Test Action Group (iJTAG) standards, as taught by Khurana’644, in order to provide non-intrusive software-based embedded instrumentation which executes out of hardware on the circuit being test and is not limited by physical probes (see Col. 1, lines 41-46) and it has been held to be within general skill of a work in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over DODDI’504.
As to claim 10, DODDI’504 discloses all the claimed limitations except the interconnect layer comprises a hybrid copper bonding (HCB) interconnect layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify DODDI’504’s invention to comprise a hybrid copper bonding (HCB) interconnect layer since it has been held to be within general skill of a work in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Das Sharma et al. (U.S. Publication No. 2022/0334995 A1) discloses parameter exchange for a die-to-die interconnect.
Wu et al. (U.S. Publication No. 2020/0320031 A1) discloses a fabric composed of point-to-point links that interconnect a set of components.
Sharma et al. (U.S. Publication No. 2024/0020259 A1) discloses an interconnect interface to enable communication with an off-package device over a link including multiple lanes.
Iyer et al. (U.S. Publication No. 2022/0350698 A1) discloses multichip package link error detection.
Wagh et al. (U.S. Publication No. 2016/0283429 A1) discloses a system-on-chip divided into hard IP blocks with fixed routing and soft IP blocks with flexible routing.
Choudhary et al. (U.S. Publication No. 2022/0342841 A1) discloses a die-to-die adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer block using a second interface.
Lanka et al. (U.S. Publication No. 2020/0394150 A1) discloses an adapter including a first interface to couple a particular device where link layer data is communicated over first interface and second interface to couple to a physical layer device.
Mishra et al. (U.S. Publication No. 2022/0156220 A1) discloses alternate sideband signaling in a PCIe link.
Ware (U.S. Publication No. 2016/0328008 A1) discloses dynamically changing data access bandwidth by selectively enabling and disabling data links.
DODDI et al. (U.S. Publication No. 2024/0345976 A1) discloses single clock lane operation for a main band of a die-to-die connection.
SRIVASTAVA et al. (U.S. Publication No. 2025/0086132 A1) discloses an apparatus for configuring an interconnect link between chiplets.
Pasdast et al. (U.S. Publication No. 2022/0271912 A1) discloses clock phase management for die-to-die (D2D) interconnect.
Spruth et al. (U.S. Publication No. 2026/0024607 A1) discloses memory built-in-self-test with enhanced fault counter.
Desineni et al. (U.S. Publication No. 2009/0132976 A1) discloses a method for testing an integrated circuit and analyzing test data.
Chen et al. (U.S. Publication No. 2004/0128406 A1) discloses test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-ports RAMs.
Das Sharma et al. (U.S. Publication No. 2021/0097015 A1) discloses extending multichip package link off package.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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/TITUS WONG/Primary Examiner, Art Unit 2181
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